* [PATCH v2] hw/riscv: Fix OT IBEX reset vector
@ 2021-04-20 8:00 Alexander Wagner
2021-04-21 0:00 ` Alistair Francis
0 siblings, 1 reply; 3+ messages in thread
From: Alexander Wagner @ 2021-04-20 8:00 UTC (permalink / raw)
To: qemu-devel; +Cc: kbastian, Alistair Francis, palmer, Alexander Wagner, sagark
The IBEX documentation [1] specifies the reset vector to be "the most
significant 3 bytes of the boot address and the reset value (0x80) as
the least significant byte".
[1] https://github.com/lowRISC/ibex/blob/master/doc/03_reference/exception_interrupts.rst
Signed-off-by: Alexander Wagner <alexander.wagner@ulal.de>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/opentitan.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index e168bffe69..ca4c1be6f6 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -120,7 +120,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
&error_abort);
object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
&error_abort);
- object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8090, &error_abort);
+ object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8080, &error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
/* Boot ROM */
--
2.25.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v2] hw/riscv: Fix OT IBEX reset vector
2021-04-20 8:00 [PATCH v2] hw/riscv: Fix OT IBEX reset vector Alexander Wagner
@ 2021-04-21 0:00 ` Alistair Francis
2021-04-21 7:36 ` Alexander Wagner
0 siblings, 1 reply; 3+ messages in thread
From: Alistair Francis @ 2021-04-21 0:00 UTC (permalink / raw)
To: Alexander Wagner
Cc: Bastian Koppelmann, Palmer Dabbelt, Alistair Francis,
qemu-devel@nongnu.org Developers, Sagar Karandikar
On Tue, Apr 20, 2021 at 6:01 PM Alexander Wagner
<alexander.wagner@ulal.de> wrote:
>
> The IBEX documentation [1] specifies the reset vector to be "the most
> significant 3 bytes of the boot address and the reset value (0x80) as
> the least significant byte".
>
> [1] https://github.com/lowRISC/ibex/blob/master/doc/03_reference/exception_interrupts.rst
>
> Signed-off-by: Alexander Wagner <alexander.wagner@ulal.de>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> hw/riscv/opentitan.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> index e168bffe69..ca4c1be6f6 100644
> --- a/hw/riscv/opentitan.c
> +++ b/hw/riscv/opentitan.c
> @@ -120,7 +120,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
> &error_abort);
> object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
> &error_abort);
> - object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8090, &error_abort);
> + object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8080, &error_abort);
> sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
>
> /* Boot ROM */
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2021-04-20 8:00 [PATCH v2] hw/riscv: Fix OT IBEX reset vector Alexander Wagner
2021-04-21 0:00 ` Alistair Francis
2021-04-21 7:36 ` Alexander Wagner
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