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From: "Cédric Le Goater" <clg@kaod.org>
To: Nicholas Piggin <npiggin@gmail.com>,
	David Gibson <david@gibson.dropbear.id.au>
Cc: qemu-ppc@nongnu.org, Greg Kurz <groug@kaod.org>, qemu-devel@nongnu.org
Subject: Re: [PATCH] target/ppc: Do not check for LPCR[HAIL] on power10_v1.0 CPUs
Date: Tue, 4 May 2021 13:54:39 +0200	[thread overview]
Message-ID: <850b8bb4-0e79-f5ee-ef95-a0e8d95ff9b0@kaod.org> (raw)
In-Reply-To: <1620125242.e97yybasbv.astroid@bobo.none>

On 5/4/21 12:49 PM, Nicholas Piggin wrote:
> Excerpts from Cédric Le Goater's message of May 4, 2021 7:59 pm:
>> The LPCR[HAIL] bit only applies to POWER10 DD2 CPUs. On POWER10 DD1,
>> the ail value should be extracted using the LPCR_AIL mask like on P9.
>>
>> Cc: Nicholas Piggin <npiggin@gmail.com>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> 
> Thanks for this, my oversight for not realising the P10 CPU is DD1 
> (which doesn't have HAIL).
> 
> I wonder if it could just use the POWER9 excp_model?

Yes. Why not. It does bring up another problem which is how to define
(cleanly) different characteristics for CPUs of the same POWER family.

Currently, all P10s are under POWERPC_FAMILY(POWER10). This is a base 
abstract class and definitions can not depend on the PVR. See below
what needs to be done to add a custom LPCR mask for DD2 :/

We could also simply switch P10 to DD2. I would favor that instead of 
adding complexity. 

David, what is your opinion on this ? 

Thank,

C. 


Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 target/ppc/cpu-models.c |   13 +++++++++++--
 target/ppc/cpu-models.h |    1 +
 2 files changed, 12 insertions(+), 2 deletions(-)

Index: qemu-powernv-6.1.git/target/ppc/cpu-models.c
===================================================================
--- qemu-powernv-6.1.git.orig/target/ppc/cpu-models.c
+++ qemu-powernv-6.1.git/target/ppc/cpu-models.c
@@ -32,7 +32,7 @@
 /* PowerPC CPU definitions                                                 */
 #define POWERPC_DEF_PREFIX(pvr, svr, type)                                  \
     glue(glue(glue(glue(pvr, _), svr), _), type)
-#define POWERPC_DEF_SVR(_name, _desc, _pvr, _svr, _type)                    \
+#define __POWERPC_DEF_SVR(_name, _desc, _pvr, _svr, _type, _lpcr)           \
     static void                                                             \
     glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_class_init)            \
     (ObjectClass *oc, void *data)                                           \
@@ -40,6 +40,7 @@
         DeviceClass *dc = DEVICE_CLASS(oc);                                 \
         PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);                       \
                                                                             \
+        pcc->lpcr_mask    |= _lpcr;                                         \
         pcc->pvr          = _pvr;                                           \
         pcc->svr          = _svr;                                           \
         dc->desc          = _desc;                                          \
@@ -63,6 +64,12 @@
     type_init(                                                              \
         glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_register_types))
 
+#define POWERPC_DEF_SVR(_name, _desc, _pvr, _svr, _type)                    \
+    __POWERPC_DEF_SVR(_name, _desc, _pvr, _svr, _type, 0)
+
+#define POWERPC_DEF_LPCR(_name, _pvr, _type, _desc, _lpcr)                  \
+    __POWERPC_DEF_SVR(_name, _desc, _pvr, POWERPC_SVR_NONE, _type, _lpcr)
+
 #define POWERPC_DEF(_name, _pvr, _type, _desc)                              \
     POWERPC_DEF_SVR(_name, _desc, _pvr, POWERPC_SVR_NONE, _type)
 
@@ -776,6 +783,8 @@
                 "POWER9 v2.0")
     POWERPC_DEF("power10_v1.0",  CPU_POWERPC_POWER10_DD1,            POWER10,
                 "POWER10 v1.0")
+    POWERPC_DEF_LPCR("power10_v2.0",  CPU_POWERPC_POWER10_DD20,      POWER10,
+                     "POWER10 v2.0", LPCR_HAIL)
 #endif /* defined (TARGET_PPC64) */
 
 /***************************************************************************/
@@ -952,7 +961,7 @@ PowerPCCPUAlias ppc_cpu_aliases[] = {
     { "power8", "power8_v2.0" },
     { "power8nvl", "power8nvl_v1.0" },
     { "power9", "power9_v2.0" },
-    { "power10", "power10_v1.0" },
+    { "power10", "power10_v2.0" },
 #endif
 
     /* Generic PowerPCs */
Index: qemu-powernv-6.1.git/target/ppc/cpu-models.h
===================================================================
--- qemu-powernv-6.1.git.orig/target/ppc/cpu-models.h
+++ qemu-powernv-6.1.git/target/ppc/cpu-models.h
@@ -375,6 +375,7 @@ enum {
     CPU_POWERPC_POWER9_DD20        = 0x004E1200,
     CPU_POWERPC_POWER10_BASE       = 0x00800000,
     CPU_POWERPC_POWER10_DD1        = 0x00800100,
+    CPU_POWERPC_POWER10_DD20       = 0x00800200,
     CPU_POWERPC_970_v22            = 0x00390202,
     CPU_POWERPC_970FX_v10          = 0x00391100,
     CPU_POWERPC_970FX_v20          = 0x003C0200,


  reply	other threads:[~2021-05-04 11:56 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-04  9:59 [PATCH] target/ppc: Do not check for LPCR[HAIL] on power10_v1.0 CPUs Cédric Le Goater
2021-05-04 10:49 ` Nicholas Piggin
2021-05-04 11:54   ` Cédric Le Goater [this message]
2021-05-05  5:00     ` David Gibson

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