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[81.40.121.121]) by smtp.gmail.com with ESMTPSA id 128sm25655841wmz.43.2020.08.16.04.08.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 16 Aug 2020 04:08:26 -0700 (PDT) Subject: Re: [PATCH 13/18] hw/riscv: microchip_pfsoc: Connect a DMA controller To: Bin Meng References: <1597423256-14847-1-git-send-email-bmeng.cn@gmail.com> <1597423256-14847-14-git-send-email-bmeng.cn@gmail.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <8539f87c-02e3-b393-af27-c23c6117ff18@amsat.org> Date: Sun, 16 Aug 2020 13:08:26 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.5.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::342; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x342.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: 0 X-Spam_score: 0.0 X-Spam_bar: / X-Spam_report: (0.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=1, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , "open list:RISC-V" , Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , "qemu-devel@nongnu.org Developers" , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 8/16/20 10:57 AM, Bin Meng wrote: > Hi Philippe, > > On Sat, Aug 15, 2020 at 5:00 PM Philippe Mathieu-Daudé wrote: >> >> On 8/14/20 6:40 PM, Bin Meng wrote: >>> From: Bin Meng >>> >>> Connect a DMA controller to Microchip PolarFire SoC. Note interrupt >>> has not been connected due to missing information in the manual how >>> interrupts are routed to PLIC. >>> >>> On the Icicle Kit board, the HSS firmware utilizes the on-chip DMA >>> controller to move the 2nd stage bootloader in the system memory. >>> >>> Signed-off-by: Bin Meng >>> --- >>> >>> hw/riscv/Kconfig | 1 + >>> hw/riscv/microchip_pfsoc.c | 10 ++++++++++ >>> include/hw/riscv/microchip_pfsoc.h | 3 +++ >>> 3 files changed, 14 insertions(+) >>> >>> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig >>> index 7412db9..9323701 100644 >>> --- a/hw/riscv/Kconfig >>> +++ b/hw/riscv/Kconfig >>> @@ -55,4 +55,5 @@ config MICROCHIP_PFSOC >>> select SIFIVE >>> select UNIMP >>> select MCHP_PFSOC_MMUART >>> + select MCHP_PFSOC_DMA >>> select CADENCE_SDHCI >>> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c >>> index 7c09078..1c67cbc 100644 >>> --- a/hw/riscv/microchip_pfsoc.c >>> +++ b/hw/riscv/microchip_pfsoc.c >>> @@ -13,6 +13,7 @@ >>> * 2) eNVM (Embedded Non-Volatile Memory) >>> * 3) MMUARTs (Multi-Mode UART) >>> * 4) Cadence eMMC/SDHC controller and an SD card connected to it >>> + * 5) DMA (Direct Memory Access Controller) >>> * >>> * This board currently generates devicetree dynamically that indicates at least >>> * two harts and up to five harts. >>> @@ -71,6 +72,7 @@ static const struct MemmapEntry { >>> [MICROCHIP_PFSOC_BUSERR_UNIT4] = { 0x1704000, 0x1000 }, >>> [MICROCHIP_PFSOC_CLINT] = { 0x2000000, 0x10000 }, >>> [MICROCHIP_PFSOC_L2CC] = { 0x2010000, 0x1000 }, >>> + [MICROCHIP_PFSOC_DMA] = { 0x3000000, 0x100000 }, >>> [MICROCHIP_PFSOC_L2LIM] = { 0x8000000, 0x2000000 }, >>> [MICROCHIP_PFSOC_PLIC] = { 0xc000000, 0x4000000 }, >>> [MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 }, >>> @@ -114,6 +116,9 @@ static void microchip_pfsoc_soc_instance_init(Object *obj) >>> TYPE_RISCV_CPU_SIFIVE_U54); >>> qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR); >>> >>> + object_initialize_child(obj, "dma-controller", &s->dma, >>> + TYPE_MCHP_PFSOC_DMA); >>> + >>> object_initialize_child(obj, "sd-controller", &s->sdhci, >>> TYPE_CADENCE_SDHCI); >> >> I haven't looked at the chip specs, but maybe you can add the SD >> controller after the DMA controller so so you can directly link >> a DMA address space to it. >> > > I am not sure I understand what you meant about adding the SD > controller after the DMA controller. The Cadence SD controller has its > own built-in DMA and does not depend on this DMA controller. Ah OK. What I'm concerned about is the SD controller do its DMA access in a proper DMA address space. > > Regards, > Bin >