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[88.21.205.111]) by smtp.gmail.com with ESMTPSA id a12sm5366227edu.89.2020.11.23.08.55.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 23 Nov 2020 08:55:34 -0800 (PST) Subject: Re: [Bug 1905297] [NEW] Zynq7000 UART clock reset initialization To: qemu-devel@nongnu.org, Michael Peter , Damien Hedde References: <160614967524.17013.9714069541645314856.malonedeb@wampee.canonical.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <85b90548-75d2-4402-674a-cabd1a517e2a@amsat.org> Date: Mon, 23 Nov 2020 17:55:33 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.4.0 MIME-Version: 1.0 In-Reply-To: <160614967524.17013.9714069541645314856.malonedeb@wampee.canonical.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::634; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x634.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bug 1905297 <1905297@bugs.launchpad.net>, qemu-arm Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Hi Michael, On 11/23/20 5:41 PM, Michael Peter wrote: > Public bug reported: > > Hello, > > we have come across a strange behavior in the Zynq7000 model of Qemu > that seems to have been introduced between 5.0.0 and 5.1.0. > > > The reset values of the SLCR register, in particular those for UART_CLK_CTRL, are such that > the UARTs should find functional clocks. Up to 5.0.0 this was also the behavior that was > implemented in QEMU. > > Starting in 5.1.0, we found that - despite correct reset values [1] - the UARTs are non-functional > upon reset. Some investigation revealed that the cause for that is that the corresponding > clocks are not properly initialized. > > Between 5.0.0 and 5.1.0, there are three commits that touch the Zynq > UART clocks [2]. The last of them [3] triggers the faulty behavior. > > Attached is a patch that applies 5.2.0-rc2 and yields a functional UART. We surmise that the > underlying device release issue runs much deeper, so it is only meant to identify the issue. > > > [1] hw/misc/zynq_slcr.c > static void zynq_slcr_reset_init(Object *obj, ResetType type) > s->regs[R_UART_CLK_CTRL] = 0x00003F03; > [2] 38867cb7ec90..5b49a34c6800 > [3] commit 5b49a34c6800d0cb917f959d8e75e5775f0fac3f (refs/bisect/bad) > Author: Damien Hedde > Date: Mon Apr 6 15:52:50 2020 +0200 > > ** Affects: qemu > Importance: Undecided > Status: New > > ** Patch added: "0001-Initialize-Zynq7000-UART-clocks-on-reset.patch" > https://bugs.launchpad.net/bugs/1905297/+attachment/5437267/+files/0001-Initialize-Zynq7000-UART-clocks-on-reset.patch > Can you post your patch to the mailing list please? See: https://wiki.qemu.org/Contribute/SubmitAPatch#Do_not_send_as_an_attachment Note, you must sign your patch with a Signed-off-by: line, see: https://wiki.qemu.org/Contribute/SubmitAPatch#Patch_emails_must_include_a_Signed-off-by:_line Regards, Phil. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F0EDC63777 for ; Mon, 23 Nov 2020 17:06:18 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6DFC2206E3 for ; Mon, 23 Nov 2020 17:06:17 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6DFC2206E3 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bugs.launchpad.net Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:53658 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1khFI8-0004SD-EG for qemu-devel@archiver.kernel.org; Mon, 23 Nov 2020 12:06:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58972) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1khFCz-0007Ep-IT for qemu-devel@nongnu.org; Mon, 23 Nov 2020 12:01:03 -0500 Received: from indium.canonical.com ([91.189.90.7]:45050) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1khFCr-0003Dv-6N for qemu-devel@nongnu.org; Mon, 23 Nov 2020 12:00:57 -0500 Received: from loganberry.canonical.com ([91.189.90.37]) by indium.canonical.com with esmtp (Exim 4.86_2 #2 (Debian)) id 1khFCm-0003io-HD for ; Mon, 23 Nov 2020 17:00:44 +0000 Received: from loganberry.canonical.com (localhost [127.0.0.1]) by loganberry.canonical.com (Postfix) with ESMTP id 80E782E804B for ; Mon, 23 Nov 2020 17:00:44 +0000 (UTC) MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Date: Mon, 23 Nov 2020 16:55:33 -0000 From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <1905297@bugs.launchpad.net> To: qemu-devel@nongnu.org X-Launchpad-Notification-Type: bug X-Launchpad-Bug: product=qemu; status=New; importance=Undecided; assignee=None; X-Launchpad-Bug-Information-Type: Public X-Launchpad-Bug-Private: no X-Launchpad-Bug-Security-Vulnerability: no X-Launchpad-Bug-Commenters: michaelpeter philmd X-Launchpad-Bug-Reporter: Michael Peter (michaelpeter) X-Launchpad-Bug-Modifier: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9_=28philmd?= =?utf-8?q?=29?= References: <160614967524.17013.9714069541645314856.malonedeb@wampee.canonical.com> Message-ID: <85b90548-75d2-4402-674a-cabd1a517e2a@amsat.org> Subject: Re: [Bug 1905297] [NEW] Zynq7000 UART clock reset initialization X-Launchpad-Message-Rationale: Subscriber (QEMU) @qemu-devel-ml X-Launchpad-Message-For: qemu-devel-ml Precedence: bulk X-Generated-By: Launchpad (canonical.com); Revision="c35ff22711d15549e2303ae18ae521fd91f6bf00"; Instance="production" X-Launchpad-Hash: 6f607a7473242c6af332f23f566d0d64d8cfde8a Received-SPF: none client-ip=91.189.90.7; envelope-from=bounces@canonical.com; helo=indium.canonical.com X-Spam_score_int: -65 X-Spam_score: -6.6 X-Spam_bar: ------ X-Spam_report: (-6.6 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: Bug 1905297 <1905297@bugs.launchpad.net> Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Message-ID: <20201123165533.2rJcYjjqHMwE2iNYuPHhSOU5KFvsxZlzGNzt21tNUxc@z> Hi Michael, On 11/23/20 5:41 PM, Michael Peter wrote: > Public bug reported: > = > Hello, > = > we have come across a strange behavior in the Zynq7000 model of Qemu > that seems to have been introduced between 5.0.0 and 5.1.0. > = > = > The reset values of the SLCR register, in particular those for UART_CLK_C= TRL, are such that > the UARTs should find functional clocks. Up to 5.0.0 this was also the be= havior that was > implemented in QEMU. > = > Starting in 5.1.0, we found that - despite correct reset values [1] - the= UARTs are non-functional > upon reset. Some investigation revealed that the cause for that is that t= he corresponding > clocks are not properly initialized. > = > Between 5.0.0 and 5.1.0, there are three commits that touch the Zynq > UART clocks [2]. The last of them [3] triggers the faulty behavior. > = > Attached is a patch that applies 5.2.0-rc2 and yields a functional UART. = We surmise that the > underlying device release issue runs much deeper, so it is only meant to = identify the issue. > = > = > [1] hw/misc/zynq_slcr.c > static void zynq_slcr_reset_init(Object *obj, ResetType type) > s->regs[R_UART_CLK_CTRL] =3D 0x00003F03; > [2] 38867cb7ec90..5b49a34c6800 > [3] commit 5b49a34c6800d0cb917f959d8e75e5775f0fac3f (refs/bisect/bad) > Author: Damien Hedde > Date: Mon Apr 6 15:52:50 2020 +0200 > = > ** Affects: qemu > Importance: Undecided > Status: New > = > ** Patch added: "0001-Initialize-Zynq7000-UART-clocks-on-reset.patch" > https://bugs.launchpad.net/bugs/1905297/+attachment/5437267/+files/000= 1-Initialize-Zynq7000-UART-clocks-on-reset.patch > = Can you post your patch to the mailing list please? See: https://wiki.qemu.org/Contribute/SubmitAPatch#Do_not_send_as_an_attachment Note, you must sign your patch with a Signed-off-by: line, see: https://wiki.qemu.org/Contribute/SubmitAPatch#Patch_emails_must_include_a_S= igned-off-by:_line Regards, Phil. -- = You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1905297 Title: Zynq7000 UART clock reset initialization Status in QEMU: New Bug description: Hello, we have come across a strange behavior in the Zynq7000 model of Qemu that seems to have been introduced between 5.0.0 and 5.1.0. = The reset values of the SLCR register, in particular those for UART_CLK_C= TRL, are such that the UARTs should find functional clocks. Up to 5.0.0 this was also the be= havior that was implemented in QEMU. Starting in 5.1.0, we found that - despite correct reset values [1] - the= UARTs are non-functional upon reset. Some investigation revealed that the cause for that is that t= he corresponding clocks are not properly initialized. Between 5.0.0 and 5.1.0, there are three commits that touch the Zynq UART clocks [2]. The last of them [3] triggers the faulty behavior. Attached is a patch that applies 5.2.0-rc2 and yields a functional UART. = We surmise that the underlying device release issue runs much deeper, so it is only meant to = identify the issue. [1] hw/misc/zynq_slcr.c static void zynq_slcr_reset_init(Object *obj, ResetType type) s->regs[R_UART_CLK_CTRL] =3D 0x00003F03; [2] 38867cb7ec90..5b49a34c6800 [3] commit 5b49a34c6800d0cb917f959d8e75e5775f0fac3f (refs/bisect/bad) Author: Damien Hedde Date: Mon Apr 6 15:52:50 2020 +0200 To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1905297/+subscriptions