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Thu, 2 Apr 2020 16:47:02 +0000 (UTC) Received: from [10.36.112.58] (ovpn-112-58.ams2.redhat.com [10.36.112.58]) by smtp.corp.redhat.com (Postfix) with ESMTPS id BF85D9B924; Thu, 2 Apr 2020 16:46:50 +0000 (UTC) Subject: Re: [RFC v6 00/24] vSMMUv3/pSMMUv3 2 stage VFIO integration To: Zhangfei Gao , eric.auger.pro@gmail.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, mst@redhat.com, alex.williamson@redhat.com, jacob.jun.pan@linux.intel.com, yi.l.liu@intel.com References: <20200320165840.30057-1-eric.auger@redhat.com> <73b1c3e1-a418-f57c-d949-261250d6a79b@linaro.org> From: Auger Eric Message-ID: <86c0b1e4-8073-1644-f420-0b548c8f8895@redhat.com> Date: Thu, 2 Apr 2020 18:46:49 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jean-philippe@linaro.org, tnowicki@marvell.com, maz@kernel.org, shameerali.kolothum.thodi@huawei.com, peterx@redhat.com, bbhushan2@marvell.com, will@kernel.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Hi Zhangfei, On 3/31/20 10:24 AM, Zhangfei Gao wrote: > Hi, Eric >=20 > On 2020/3/31 =E4=B8=8B=E5=8D=884:12, Auger Eric wrote: >> Hi Zhangfei, >> >> On 3/31/20 8:42 AM, Zhangfei Gao wrote: >>> Hi, Eric >>> >>> On 2020/3/21 =E4=B8=8A=E5=8D=8812:58, Eric Auger wrote: >>>> Up to now vSMMUv3 has not been integrated with VFIO. VFIO >>>> integration requires to program the physical IOMMU consistently >>>> with the guest mappings. However, as opposed to VTD, SMMUv3 has >>>> no "Caching Mode" which allows easy trapping of guest mappings. >>>> This means the vSMMUV3 cannot use the same VFIO integration as VTD. >>>> >>>> However SMMUv3 has 2 translation stages. This was devised with >>>> virtualization use case in mind where stage 1 is "owned" by the >>>> guest whereas the host uses stage 2 for VM isolation. >>>> >>>> This series sets up this nested translation stage. It only works >>>> if there is one physical SMMUv3 used along with QEMU vSMMUv3 (in >>>> other words, it does not work if there is a physical SMMUv2). >>>> >>>> - We force the host to use stage 2 instead of stage 1, when we >>>> =C2=A0=C2=A0=C2=A0 detect a vSMMUV3 is behind a VFIO device. For a VFI= O device >>>> =C2=A0=C2=A0=C2=A0 without any virtual IOMMU, we still use stage 1 as = many existing >>>> =C2=A0=C2=A0=C2=A0 SMMUs expect this behavior. >>>> - We use PCIPASIDOps to propage guest stage1 config changes on >>>> =C2=A0=C2=A0=C2=A0 STE (Stream Table Entry) changes. >>>> - We implement a specific UNMAP notifier that conveys guest >>>> =C2=A0=C2=A0=C2=A0 IOTLB invalidations to the host >>>> - We register MSI IOVA/GPA bindings to the host so that this latter >>>> =C2=A0=C2=A0=C2=A0 can build a nested stage translation >>>> - As the legacy MAP notifier is not called anymore, we must make >>>> =C2=A0=C2=A0=C2=A0 sure stage 2 mappings are set. This is achieved thr= ough another >>>> =C2=A0=C2=A0=C2=A0 prereg memory listener. >>>> - Physical SMMU stage 1 related faults are reported to the guest >>>> =C2=A0=C2=A0=C2=A0 via en eventfd mechanism and exposed trhough a dedi= cated VFIO-PCI >>>> =C2=A0=C2=A0=C2=A0 region. Then they are reinjected into the guest. >>>> >>>> Best Regards >>>> >>>> Eric >>>> >>>> This series can be found at: >>>> https://github.com/eauger/qemu/tree/v4.2.0-2stage-rfcv6 >>>> >>>> Kernel Dependencies: >>>> [1] [PATCH v10 00/11] SMMUv3 Nested Stage Setup (VFIO part) >>>> [2] [PATCH v10 00/13] SMMUv3 Nested Stage Setup (IOMMU part) >>>> branch at: >>>> https://github.com/eauger/linux/tree/will-arm-smmu-updates-2stage-v10 >>> Really appreciated that you re-start this work. >>> >>> I tested your branch and some update. >>> >>> Guest: https://github.com/Linaro/linux-kernel-warpdrive/tree/sva-devel >>> >>> Host: >>> https://github.com/eauger/linux/tree/will-arm-smmu-updates-2stage-v10 >>> >>> qemu: https://github.com/eauger/qemu/tree/v4.2.0-2stage-rfcv6 >>> >>> >>> The guest I am using is contains Jean's sva patches. >>> Since currently they are many patch conflict, so use two different tree= . >>> >>> Result >>> No-sva mode works. >>> This mode, guest directly get physical address via ioctl. >> OK thanks for testing >>> While vSVA can not work, there are still much work to do. >>> I am trying to SVA mode, and it fails, so choose no-sva instead. >>> iommu_dev_enable_feature(parent, IOMMU_DEV_FEAT_SVA) >> Indeed I assume there are plenty of things missing to make vSVM work on >> ARM (iommu, vfio, QEMU). I am currently reviewing Jacob and Yi's kernel >> and QEMU series on Intel side. After that, I will come back to you to >> help. Also vSMMUv3 does not support multiple contexts at the moment. I >> will add this soon. >> >> >> Still the problem I have is testing. Any suggestion welcome. >> >> > To make sure > Do you mean you need a environment for testing? >=20 > How about Hisilicon kunpeng920, arm64 platform supporting SVA in host now= . > There is such a platform in linaro mlab that I think we can share. > Currently I am testing with uacce, > By testing a user driver (hisi zip accelerator) in guest, we can test > vSVA and PASID easily. Sorry for the delay. I am currently investigating if this could be possible. Thank you for the suggestion! Best Regards Eric >=20 > Thanks >=20