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X-Received-From: 2a00:1450:4864:20::341 Subject: Re: [Qemu-devel] [PATCH for-4.2 11/24] target/arm: Add the hypervisor virtual counter X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, beata.michalska@linaro.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Richard Henderson writes: > Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e > --- > target/arm/cpu-qom.h | 1 + > target/arm/cpu.h | 11 +++++---- > target/arm/cpu.c | 2 ++ > target/arm/helper.c | 57 ++++++++++++++++++++++++++++++++++++++++++++ > 4 files changed, 66 insertions(+), 5 deletions(-) > > diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h > index 2049fa9612..43fc8296db 100644 > --- a/target/arm/cpu-qom.h > +++ b/target/arm/cpu-qom.h > @@ -76,6 +76,7 @@ void arm_gt_ptimer_cb(void *opaque); > void arm_gt_vtimer_cb(void *opaque); > void arm_gt_htimer_cb(void *opaque); > void arm_gt_stimer_cb(void *opaque); > +void arm_gt_hvtimer_cb(void *opaque); > > #define ARM_AFF0_SHIFT 0 > #define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT) > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index e37008a4f7..bba4e1f984 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -144,11 +144,12 @@ typedef struct ARMGenericTimer { > uint64_t ctl; /* Timer Control register */ > } ARMGenericTimer; > > -#define GTIMER_PHYS 0 > -#define GTIMER_VIRT 1 > -#define GTIMER_HYP 2 > -#define GTIMER_SEC 3 > -#define NUM_GTIMERS 4 > +#define GTIMER_PHYS 0 > +#define GTIMER_VIRT 1 > +#define GTIMER_HYP 2 > +#define GTIMER_SEC 3 > +#define GTIMER_HYPVIRT 4 > +#define NUM_GTIMERS 5 > > typedef struct { > uint64_t raw_tcr; > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index 1959467fdc..90352decc5 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -1218,6 +1218,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) > arm_gt_htimer_cb, cpu); > cpu->gt_timer[GTIMER_SEC] =3D timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_S= CALE, > arm_gt_stimer_cb, cpu); > + cpu->gt_timer[GTIMER_HYPVIRT] =3D timer_new(QEMU_CLOCK_VIRTUAL, GTIM= ER_SCALE, > + arm_gt_hvtimer_cb, cpu); > #endif > > cpu_exec_realizefn(cs, &local_err); > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 3124d682a2..329548e45d 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -2527,6 +2527,7 @@ static uint64_t gt_tval_read(CPUARMState *env, cons= t ARMCPRegInfo *ri, > > switch (timeridx) { > case GTIMER_VIRT: > + case GTIMER_HYPVIRT: > offset =3D gt_virt_cnt_offset(env); > break; > } > @@ -2543,6 +2544,7 @@ static void gt_tval_write(CPUARMState *env, const A= RMCPRegInfo *ri, > > switch (timeridx) { > case GTIMER_VIRT: > + case GTIMER_HYPVIRT: > offset =3D gt_virt_cnt_offset(env); > break; > } > @@ -2698,6 +2700,34 @@ static void gt_sec_ctl_write(CPUARMState *env, con= st ARMCPRegInfo *ri, > gt_ctl_write(env, ri, GTIMER_SEC, value); > } > > +static void gt_hv_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) > +{ > + gt_timer_reset(env, ri, GTIMER_HYPVIRT); > +} > + > +static void gt_hv_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, > + uint64_t value) > +{ > + gt_cval_write(env, ri, GTIMER_HYPVIRT, value); > +} > + > +static uint64_t gt_hv_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) > +{ > + return gt_tval_read(env, ri, GTIMER_HYPVIRT); > +} > + > +static void gt_hv_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, > + uint64_t value) > +{ > + gt_tval_write(env, ri, GTIMER_HYPVIRT, value); > +} > + > +static void gt_hv_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, > + uint64_t value) > +{ > + gt_ctl_write(env, ri, GTIMER_HYPVIRT, value); > +} > + > void arm_gt_ptimer_cb(void *opaque) > { > ARMCPU *cpu =3D opaque; > @@ -2726,6 +2756,13 @@ void arm_gt_stimer_cb(void *opaque) > gt_recalc_timer(cpu, GTIMER_SEC); > } > > +void arm_gt_hvtimer_cb(void *opaque) > +{ > + ARMCPU *cpu =3D opaque; > + > + gt_recalc_timer(cpu, GTIMER_HYPVIRT); > +} > + > static const ARMCPRegInfo generic_timer_cp_reginfo[] =3D { > /* Note that CNTFRQ is purely reads-as-written for the benefit > * of software; writing it doesn't actually change the timer frequen= cy. > @@ -6852,6 +6889,26 @@ void register_cp_regs_for_features(ARMCPU *cpu) > .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 = =3D 1, > .access =3D PL2_RW, .writefn =3D vmsa_tcr_ttbr_el2_write, > .fieldoffset =3D offsetof(CPUARMState, cp15.ttbr1_el[2]) }, > +#ifndef CONFIG_USER_ONLY > + { .name =3D "CNTHV_CVAL_EL2", .state =3D ARM_CP_STATE_AA64, > + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 3, .opc2 = =3D 2, > + .fieldoffset =3D > + offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYPVIRT].cva= l), > + .type =3D ARM_CP_IO, .access =3D PL2_RW, > + .writefn =3D gt_hv_cval_write, .raw_writefn =3D raw_write = }, > + { .name =3D "CNTHV_TVAL_EL2", .state =3D ARM_CP_STATE_BOTH, > + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 3, .opc2 = =3D 0, > + .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL2_RW, > + .resetfn =3D gt_hv_timer_reset, > + .readfn =3D gt_hv_tval_read, .writefn =3D gt_hv_tval_write= }, > + { .name =3D "CNTHV_CTL_EL2", .state =3D ARM_CP_STATE_BOTH, > + .type =3D ARM_CP_IO, > + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 3, .opc2 = =3D 1, > + .access =3D PL2_RW, > + .fieldoffset =3D > + offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYPVIRT].ctl= ), > + .writefn =3D gt_hv_ctl_write, .raw_writefn =3D raw_write }, > +#endif > REGINFO_SENTINEL > }; > define_arm_cp_regs(cpu, vhe_reginfo); -- Alex Benn=C3=A9e