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X-Received-From: 2a00:1450:4864:20::442 Subject: Re: [Qemu-devel] [PATCH for-4.2 10/24] target/arm: Update CNTVCT_EL0 for VHE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, beata.michalska@linaro.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Richard Henderson writes: > The virtual offset may be 0 depending on EL, E2H and TGE. > > Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e > --- > target/arm/helper.c | 40 +++++++++++++++++++++++++++++++++++++--- > 1 file changed, 37 insertions(+), 3 deletions(-) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index da2e0627b2..3124d682a2 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -2484,9 +2484,31 @@ static uint64_t gt_cnt_read(CPUARMState *env, cons= t ARMCPRegInfo *ri) > return gt_get_countervalue(env); > } > > +static uint64_t gt_virt_cnt_offset(CPUARMState *env) > +{ > + uint64_t hcr; > + > + switch (arm_current_el(env)) { > + case 2: > + hcr =3D arm_hcr_el2_eff(env); > + if (hcr & HCR_E2H) { > + return 0; > + } > + break; > + case 0: > + hcr =3D arm_hcr_el2_eff(env); > + if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) { > + return 0; > + } > + break; > + } > + > + return env->cp15.cntvoff_el2; > +} > + > static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *r= i) > { > - return gt_get_countervalue(env) - env->cp15.cntvoff_el2; > + return gt_get_countervalue(env) - gt_virt_cnt_offset(env); > } > > static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, > @@ -2501,7 +2523,13 @@ static void gt_cval_write(CPUARMState *env, const = ARMCPRegInfo *ri, > static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri, > int timeridx) > { > - uint64_t offset =3D timeridx =3D=3D GTIMER_VIRT ? env->cp15.cntvoff_= el2 : 0; > + uint64_t offset =3D 0; > + > + switch (timeridx) { > + case GTIMER_VIRT: > + offset =3D gt_virt_cnt_offset(env); > + break; > + } > > return (uint32_t)(env->cp15.c14_timer[timeridx].cval - > (gt_get_countervalue(env) - offset)); > @@ -2511,7 +2539,13 @@ static void gt_tval_write(CPUARMState *env, const = ARMCPRegInfo *ri, > int timeridx, > uint64_t value) > { > - uint64_t offset =3D timeridx =3D=3D GTIMER_VIRT ? env->cp15.cntvoff_= el2 : 0; > + uint64_t offset =3D 0; > + > + switch (timeridx) { > + case GTIMER_VIRT: > + offset =3D gt_virt_cnt_offset(env); > + break; > + } > > trace_arm_gt_tval_write(timeridx, value); > env->cp15.c14_timer[timeridx].cval =3D gt_get_countervalue(env) - of= fset + -- Alex Benn=C3=A9e