From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46119) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aTr9C-0007Ah-OD for qemu-devel@nongnu.org; Thu, 11 Feb 2016 08:19:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aTr9A-0004k6-Nr for qemu-devel@nongnu.org; Thu, 11 Feb 2016 08:19:02 -0500 Received: from mail-wm0-x22c.google.com ([2a00:1450:400c:c09::22c]:33627) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aTr9A-0004jz-FG for qemu-devel@nongnu.org; Thu, 11 Feb 2016 08:19:00 -0500 Received: by mail-wm0-x22c.google.com with SMTP id g62so20943596wme.0 for ; Thu, 11 Feb 2016 05:19:00 -0800 (PST) References: <1454059965-23402-1-git-send-email-a.rigo@virtualopensystems.com> <1454059965-23402-6-git-send-email-a.rigo@virtualopensystems.com> From: Alex =?utf-8?Q?Benn=C3=A9e?= In-reply-to: <1454059965-23402-6-git-send-email-a.rigo@virtualopensystems.com> Date: Thu, 11 Feb 2016 13:18:57 +0000 Message-ID: <8760xvbd1a.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [RFC v7 05/16] softmmu: Add new TLB_EXCL flag List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alvise Rigo Cc: mttcg@listserver.greensocs.com, claudio.fontana@huawei.com, qemu-devel@nongnu.org, pbonzini@redhat.com, jani.kokkonen@huawei.com, tech@virtualopensystems.com, rth@twiddle.net Alvise Rigo writes: > Add a new TLB flag to force all the accesses made to a page to follow > the slow-path. > > The TLB entries referring guest pages with the DIRTY_MEMORY_EXCLUSIVE > bit clean will have this flag set. > > Suggested-by: Jani Kokkonen > Suggested-by: Claudio Fontana > Signed-off-by: Alvise Rigo > --- > include/exec/cpu-all.h | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h > index 83b1781..f8d8feb 100644 > --- a/include/exec/cpu-all.h > +++ b/include/exec/cpu-all.h > @@ -277,6 +277,14 @@ CPUArchState *cpu_copy(CPUArchState *env); > #define TLB_NOTDIRTY (1 << 4) > /* Set if TLB entry is an IO callback. */ > #define TLB_MMIO (1 << 5) > +/* Set if TLB entry references a page that requires exclusive access. */ > +#define TLB_EXCL (1 << 6) > + > +/* Do not allow a TARGET_PAGE_MASK which covers one or more bits defined > + * above. */ > +#if TLB_EXCL >= TARGET_PAGE_SIZE > +#error TARGET_PAGE_MASK covering the low bits of the TLB virtual address > +#endif > > void dump_exec_info(FILE *f, fprintf_function cpu_fprintf); > void dump_opcount_info(FILE *f, fprintf_function cpu_fprintf); Reviewed-by: Alex Bennée -- Alex Bennée