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X-Received-From: 2a00:1450:4864:20::342 Subject: Re: [Qemu-devel] [PATCH for-4.2 08/24] target/arm: Add CONTEXTIDR_EL2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, beata.michalska@linaro.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Richard Henderson writes: > Not all of the breakpoint types are supported, but those that > only examine contextidr are extended to support the new register. > > Signed-off-by: Richard Henderson > --- > target/arm/debug_helper.c | 50 +++++++++++++++++++++++++++++---------- > target/arm/helper.c | 11 +++++++++ > 2 files changed, 49 insertions(+), 12 deletions(-) > > diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c > index dde80273ff..2e3e90c6a5 100644 > --- a/target/arm/debug_helper.c > +++ b/target/arm/debug_helper.c > @@ -20,6 +20,7 @@ static bool linked_bp_matches(ARMCPU *cpu, int lbn) > int ctx_cmps =3D extract32(cpu->dbgdidr, 20, 4); > int bt; > uint32_t contextidr; > + uint64_t hcr_el2; > > /* > * Links to unimplemented or non-context aware breakpoints are > @@ -40,24 +41,44 @@ static bool linked_bp_matches(ARMCPU *cpu, int lbn) > } > > bt =3D extract64(bcr, 20, 4); > - > - /* > - * We match the whole register even if this is AArch32 using the > - * short descriptor format (in which case it holds both PROCID and A= SID), > - * since we don't implement the optional v7 context ID masking. > - */ > - contextidr =3D extract64(env->cp15.contextidr_el[1], 0, 32); > + hcr_el2 =3D arm_hcr_el2_eff(env); > > switch (bt) { > case 3: /* linked context ID match */ > - if (arm_current_el(env) > 1) { > - /* Context matches never fire in EL2 or (AArch64) EL3 */ > + switch (arm_current_el(env)) { > + default: > + /* Context matches never fire in AArch64 EL3 */ > return false; > + case 2: > + if (!(hcr_el2 & HCR_E2H)) { > + /* Context matches never fire in EL2 without E2H enabled= . */ > + return false; > + } > + contextidr =3D env->cp15.contextidr_el[2]; > + break; > + case 1: > + contextidr =3D env->cp15.contextidr_el[1]; > + break; > + case 0: > + if ((hcr_el2 & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TG= E)) { > + contextidr =3D env->cp15.contextidr_el[2]; > + } else { > + contextidr =3D env->cp15.contextidr_el[1]; > + } > + break; > } > - return (contextidr =3D=3D extract64(env->cp15.dbgbvr[lbn], 0, 32= )); > - case 5: /* linked address mismatch (reserved in AArch64) */ > + break; > + > + case 7: /* linked contextidr_el1 match */ > + contextidr =3D env->cp15.contextidr_el[1]; > + break; > + case 13: /* linked contextidr_el2 match */ > + contextidr =3D env->cp15.contextidr_el[2]; > + break; > + > case 9: /* linked VMID match (reserved if no EL2) */ > case 11: /* linked context ID and VMID match (reserved if no EL2) */ > + case 15: /* linked full context ID match */ > default: I'm wondering if a qemu_log(UNIMP) here? I guess not as we check the value a lot.... > /* > * Links to Unlinked context breakpoints must generate no > @@ -66,7 +87,12 @@ static bool linked_bp_matches(ARMCPU *cpu, int lbn) > return false; > } > > - return false; > + /* > + * We match the whole register even if this is AArch32 using the > + * short descriptor format (in which case it holds both PROCID and A= SID), > + * since we don't implement the optional v7 context ID masking. > + */ > + return contextidr =3D=3D (uint32_t)env->cp15.dbgbvr[lbn]; > } > > static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_wp) > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 0a55096770..d1bf31ab74 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -6801,6 +6801,17 @@ void register_cp_regs_for_features(ARMCPU *cpu) > define_arm_cp_regs(cpu, lor_reginfo); > } > > + if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, c= pu)) { > + static const ARMCPRegInfo vhe_reginfo[] =3D { > + { .name =3D "CONTEXTIDR_EL2", .state =3D ARM_CP_STATE_AA64, > + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 = =3D 1, > + .access =3D PL2_RW, > + .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_el[= 2]) }, > + REGINFO_SENTINEL > + }; > + define_arm_cp_regs(cpu, vhe_reginfo); > + } > + > if (cpu_isar_feature(aa64_sve, cpu)) { > define_one_arm_cp_reg(cpu, &zcr_el1_reginfo); > if (arm_feature(env, ARM_FEATURE_EL2)) { Anyway: Reviewed-by: Alex Benn=C3=A9e -- Alex Benn=C3=A9e