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Thu, 28 Jan 2021 08:13:21 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id y63sm6576685wmd.21.2021.01.28.08.13.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 08:13:19 -0800 (PST) Received: from zen (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id B0AC71FF7E; Thu, 28 Jan 2021 16:13:18 +0000 (GMT) References: <20210128092814.8676-1-cfontana@suse.de> <20210128092814.8676-19-cfontana@suse.de> <64d8385c-db22-b647-2402-3840b0e0e9b5@redhat.com> <9a51a203-f6a8-686f-7859-475537b3607a@suse.de> User-agent: mu4e 1.5.7; emacs 28.0.50 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Claudio Fontana Subject: Re: [PATCH v14 18/22] accel: introduce AccelCPUClass extending CPUClass Date: Thu, 28 Jan 2021 16:08:48 +0000 In-reply-to: <9a51a203-f6a8-686f-7859-475537b3607a@suse.de> Message-ID: <878s8dujj5.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Thomas Huth , Eduardo Habkost , Richard Henderson , Markus Armbruster , qemu-devel@nongnu.org, Roman Bolshakov , Alistair Francis , Paolo Bonzini , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Claudio Fontana writes: > On 1/28/21 2:03 PM, Philippe Mathieu-Daud=C3=A9 wrote: >> On 1/28/21 10:28 AM, Claudio Fontana wrote: >>> + >>> +#define TYPE_ACCEL_CPU "accel-" CPU_RESOLVING_TYPE >>> +#define ACCEL_CPU_NAME(name) (name "-" TYPE_ACCEL_CPU) >>> +typedef struct AccelCPUClass AccelCPUClass; >>> +DECLARE_CLASS_CHECKERS(AccelCPUClass, ACCEL_CPU, TYPE_ACCEL_CPU) >>> + >>> +typedef struct AccelCPUClass { >>> + /*< private >*/ >>> + ObjectClass parent_class; >>> + /*< public >*/ >>> + >>> + void (*cpu_class_init)(CPUClass *cc); >>> + void (*cpu_instance_init)(CPUState *cpu); >>> + void (*cpu_realizefn)(CPUState *cpu, Error **errp); >>=20 >> If we want callers to check errp, better have the prototype return >> a boolean. > > Good point, the whole errp thing is worth revisiting in the series, > there are many cases (which are basically reproduced in the refactoring f= rom existing code), > where errp is passed but is really unused. > > I am constantly internally debating whether to remove the parameter altog= ether, or to keep it in there. > > What would you suggest? I think it really depends on if we can expect the realizefn to usefully return an error message that can be read and understood by the user. I guess this comes down to how much user config is going to be checked at the point we realize the CPU? The bool returning realizefn with Error is a fairly common pattern. > >>=20 >>> +} AccelCPUClass; >>=20 >>=20 > > Thanks for looking at this, > > Claudio --=20 Alex Benn=C3=A9e