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X-Received-From: 2a00:1450:4864:20::343 Subject: Re: [Qemu-devel] [PATCH for-4.2 07/24] target/arm: Enable HCR_E2H for VHE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, beata.michalska@linaro.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Richard Henderson writes: > Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e > --- > target/arm/cpu.h | 7 ------- > target/arm/helper.c | 6 +++++- > 2 files changed, 5 insertions(+), 8 deletions(-) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index e6a76d14c6..e37008a4f7 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -1366,13 +1366,6 @@ static inline void xpsr_write(CPUARMState *env, ui= nt32_t val, uint32_t mask) > #define HCR_ATA (1ULL << 56) > #define HCR_DCT (1ULL << 57) > > -/* > - * When we actually implement ARMv8.1-VHE we should add HCR_E2H to > - * HCR_MASK and then clear it again if the feature bit is not set in > - * hcr_write(). > - */ > -#define HCR_MASK ((1ULL << 34) - 1) > - > #define SCR_NS (1U << 0) > #define SCR_IRQ (1U << 1) > #define SCR_FIQ (1U << 2) > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 3a9f35bf4b..0a55096770 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -4623,7 +4623,8 @@ static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[= ] =3D { > static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t= value) > { > ARMCPU *cpu =3D env_archcpu(env); > - uint64_t valid_mask =3D HCR_MASK; > + /* Begin with bits defined in base ARMv8.0. */ > + uint64_t valid_mask =3D MAKE_64BIT_MASK(0, 34); > > if (arm_feature(env, ARM_FEATURE_EL3)) { > valid_mask &=3D ~HCR_HCD; > @@ -4637,6 +4638,9 @@ static void hcr_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t value) > */ > valid_mask &=3D ~HCR_TSC; > } > + if (cpu_isar_feature(aa64_vh, cpu)) { > + valid_mask |=3D HCR_E2H; > + } > if (cpu_isar_feature(aa64_lor, cpu)) { > valid_mask |=3D HCR_TLOR; > } -- Alex Benn=C3=A9e