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Wed, 24 Mar 2021 04:44:57 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id j14sm2646557wrw.69.2021.03.24.04.44.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 04:44:56 -0700 (PDT) Received: from zen (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id A98681FF7E; Wed, 24 Mar 2021 11:44:55 +0000 (GMT) References: <20210323151749.21299-1-cfontana@suse.de> <20210323154639.23477-23-cfontana@suse.de> <87eeg5iivn.fsf@linaro.org> <1ba15970-749a-27c5-ef72-6468b5501f46@suse.de> User-agent: mu4e 1.5.11; emacs 28.0.50 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Claudio Fontana Subject: Re: [RFC v11 30/55] target/arm: wrap call to aarch64_sve_change_el in tcg_enabled() Date: Wed, 24 Mar 2021 11:41:32 +0000 In-reply-to: <1ba15970-749a-27c5-ef72-6468b5501f46@suse.de> Message-ID: <87blb8ixmw.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Eduardo Habkost , Richard Henderson , qemu-devel@nongnu.org, Roman Bolshakov , Paolo Bonzini , Philippe =?utf-8?Q?Mathieu-D?= =?utf-8?Q?aud=C3=A9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Claudio Fontana writes: > On 3/23/21 11:50 PM, Alex Benn=C3=A9e wrote: >>=20 >> Claudio Fontana writes: >>=20 >>> After this patch it is possible to build only kvm: >>> >>> ./configure --disable-tcg --enable-kvm > > > It's possible to build, but tests will fail until all the test-related > patches are applied. So I think there has to be a change in ordering in the series so we don't have differing failure modes as we enable. I'm not sure if that means all tests need to be fixed before the first "--disable-tcg builds" patch but I would expect at least a basic: qemu-system-aarch64 -M virt,gic=3Dhost -cpu host -accel kvm -m 2048 -net = none -nographic -kernel ~/lsrc/linux.git/builds/arm64.virt/arch/arm64/boot/= Image -append "panic=3D-1" --no-reboot works - so at least we can track if any of the additional changes cause regressions. >>=20 >> FWIW at this point we get a different failure than later on: >>=20 >> 21:10:25 [alex@aarch64-new:~/l/q/b/disable.tcg] (94e2abe0=E2=80=A6)|= =E2=80=A6 + make check-qtest >> GIT ui/keycodemapdb tests/fp/berkeley-testfloat-3 tests/fp/berke= ley-softfloat-3 meson dtc capstone slirp >> [1/19] Generating qemu-version.h with a meson_exe.py custom command >> Running test qtest-aarch64/qom-test >> qemu-system-aarch64: missing interface 'idau-interface' for object 'ma= chine' > > This one is broken by a recent commit in QEMU mainline, by removing the i= dau interface from KVM cpus. > > This is fixed by: Revert "target/arm: Restrict v8M IDAU to TCG" in the > series. The proper fix is probably to move the mps2tz machine type that brings this in to TCG only. Moving up the build chain to the revert I now get: ./qemu-system-aarch64 -M virt,gic=3Dhost -cpu host -accel kvm -m 2048 -ne= t none -nographic -kernel ~/lsrc/linux.git/builds/arm64.virt/arch/arm64/boo= t/Image -append "panic=3D-1" --no-reboot qemu-system-aarch64: Property 'virt-6.0-machine.gic' not found > >> socket_accept failed: Resource temporarily unavailable >> ** >> ERROR:../../tests/qtest/libqtest.c:319:qtest_init_without_qmp_handshak= e: assertion failed: (s->fd >=3D 0 && s->qmp_fd >=3D 0) >> ERROR qtest-aarch64/qom-test - Bail out! ERROR:../../tests/qtest/libqt= est.c:319:qtest_init_without_qmp_handshake: assertion failed: (s->fd >=3D 0= && s->qmp_fd >=3D 0) >> make: *** [Makefile.mtest:24: run-test-1] Error 1 >>=20 >>=20 >>> >>> Signed-off-by: Claudio Fontana >>> --- >>> target/arm/cpu-sysemu.c | 12 +++++++----- >>> 1 file changed, 7 insertions(+), 5 deletions(-) >>> >>> diff --git a/target/arm/cpu-sysemu.c b/target/arm/cpu-sysemu.c >>> index eb928832a9..05d6e79ad9 100644 >>> --- a/target/arm/cpu-sysemu.c >>> +++ b/target/arm/cpu-sysemu.c >>> @@ -820,11 +820,13 @@ static void arm_cpu_do_interrupt_aarch64(CPUState= *cs) >>> unsigned int cur_el =3D arm_current_el(env); >>> int rt; >>>=20=20 >>> - /* >>> - * Note that new_el can never be 0. If cur_el is 0, then >>> - * el0_a64 is is_a64(), else el0_a64 is ignored. >>> - */ >>> - aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); >>> + if (tcg_enabled()) { >>> + /* >>> + * Note that new_el can never be 0. If cur_el is 0, then >>> + * el0_a64 is is_a64(), else el0_a64 is ignored. >>> + */ >>> + aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); >>> + } >>>=20=20 >>> if (cur_el < new_el) { >>> /* Entry vector offset depends on whether the implemented EL >>=20 >>=20 --=20 Alex Benn=C3=A9e