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Wed, 12 May 2021 04:24:10 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id j7sm26110272wmi.21.2021.05.12.04.24.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 May 2021 04:24:08 -0700 (PDT) Received: from zen (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 8F1BA1FF7E; Wed, 12 May 2021 12:24:07 +0100 (BST) References: <20210508014802.892561-1-richard.henderson@linaro.org> <87bl9iyahr.fsf@linaro.org> <354c8418-9700-e98d-47b1-10e564fbeeaa@linaro.org> User-agent: mu4e 1.5.13; emacs 28.0.50 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Richard Henderson Subject: Re: [PATCH 00/72] Convert floatx80 and float128 to FloatParts Date: Wed, 12 May 2021 12:22:14 +0100 In-reply-to: <354c8418-9700-e98d-47b1-10e564fbeeaa@linaro.org> Message-ID: <87pmxwfb54.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, david@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Richard Henderson writes: > On 5/10/21 8:36 AM, Alex Benn=C3=A9e wrote: >> Richard Henderson writes: >>=20 >>> Reorg everything using QEMU_GENERIC and multiple inclusion to >>> reduce the amount of code duplication between the formats. >>> >>> The use of QEMU_GENERIC means that we need to use pointers instead >>> of structures, which means that even the smaller float formats >>> need rearranging. >>> >>> I've carried it through to completion within fpu/, so that we don't >>> have (much) of the legacy code remaining. There is some floatx80 >>> stuff in target/m68k and target/i386 that's still hanging around. >> FWIW I could enable a few more tests... > > Ah, thanks for the reminder that these were disabled. > I'll add this to my patch set for v2. > > >> ...although extF80_lt_quiet still has some failures on equality tests: > > This turns out to be a trivial typo in the tester itself: > > diff --git a/tests/fp/wrap.c.inc b/tests/fp/wrap.c.inc > index cb1bb77e4c..9ff884c140 100644 > --- a/tests/fp/wrap.c.inc > +++ b/tests/fp/wrap.c.inc > @@ -643,7 +643,7 @@ WRAP_CMP80(qemu_extF80M_eq, floatx80_eq_quiet) > WRAP_CMP80(qemu_extF80M_le, floatx80_le) > WRAP_CMP80(qemu_extF80M_lt, floatx80_lt) > WRAP_CMP80(qemu_extF80M_le_quiet, floatx80_le_quiet) > -WRAP_CMP80(qemu_extF80M_lt_quiet, floatx80_le_quiet) > +WRAP_CMP80(qemu_extF80M_lt_quiet, floatx80_lt_quiet) > #undef WRAP_CMP80 > > #define WRAP_CMP128(name, func) \o/ I did note we are missing mulAdd tests but they seem to be missing from the underlying testfloat code as well. I guess we don't care that much for the 80bit code? Is it even used by any architectures? --=20 Alex Benn=C3=A9e