* [PATCH 1/1] target/arm: Add support for cortex-m7 CPU
@ 2019-10-25 9:08 Christophe Lyon
2019-11-04 16:41 ` [PING] " Christophe Lyon
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Christophe Lyon @ 2019-10-25 9:08 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Christophe Lyon, richard.henderson
This is derived from cortex-m4 description, adding DP support and FPv5
instructions with the corresponding flags in isar and mvfr2.
Checked that it could successfully execute
vrinta.f32 s15, s15
while cortex-m4 emulation rejects it with "illegal instruction".
Signed-off-by: Christophe Lyon <christophe.lyon@linaro.org>
---
target/arm/cpu.c | 33 +++++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 13813fb..ccae849 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1954,6 +1954,37 @@ static void cortex_m4_initfn(Object *obj)
cpu->isar.id_isar6 = 0x00000000;
}
+static void cortex_m7_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ set_feature(&cpu->env, ARM_FEATURE_V7);
+ set_feature(&cpu->env, ARM_FEATURE_M);
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
+ set_feature(&cpu->env, ARM_FEATURE_VFP4);
+ cpu->midr = 0x411fc272; /* r1p2 */
+ cpu->pmsav7_dregion = 8;
+ cpu->isar.mvfr0 = 0x10110221;
+ cpu->isar.mvfr1 = 0x12000011;
+ cpu->isar.mvfr2 = 0x00000040;
+ cpu->id_pfr0 = 0x00000030;
+ cpu->id_pfr1 = 0x00000200;
+ cpu->id_dfr0 = 0x00100000;
+ cpu->id_afr0 = 0x00000000;
+ cpu->id_mmfr0 = 0x00100030;
+ cpu->id_mmfr1 = 0x00000000;
+ cpu->id_mmfr2 = 0x01000000;
+ cpu->id_mmfr3 = 0x00000000;
+ cpu->isar.id_isar0 = 0x01101110;
+ cpu->isar.id_isar1 = 0x02112000;
+ cpu->isar.id_isar2 = 0x20232231;
+ cpu->isar.id_isar3 = 0x01111131;
+ cpu->isar.id_isar4 = 0x01310132;
+ cpu->isar.id_isar5 = 0x00000000;
+ cpu->isar.id_isar6 = 0x00000000;
+}
+
static void cortex_m33_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
@@ -2538,6 +2569,8 @@ static const ARMCPUInfo arm_cpus[] = {
.class_init = arm_v7m_class_init },
{ .name = "cortex-m4", .initfn = cortex_m4_initfn,
.class_init = arm_v7m_class_init },
+ { .name = "cortex-m7", .initfn = cortex_m7_initfn,
+ .class_init = arm_v7m_class_init },
{ .name = "cortex-m33", .initfn = cortex_m33_initfn,
.class_init = arm_v7m_class_init },
{ .name = "cortex-r5", .initfn = cortex_r5_initfn },
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PING] [PATCH 1/1] target/arm: Add support for cortex-m7 CPU
2019-10-25 9:08 [PATCH 1/1] target/arm: Add support for cortex-m7 CPU Christophe Lyon
@ 2019-11-04 16:41 ` Christophe Lyon
2019-11-05 20:23 ` Peter Maydell
2019-11-04 17:08 ` Alex Bennée
2019-11-12 15:18 ` Peter Maydell
2 siblings, 1 reply; 6+ messages in thread
From: Christophe Lyon @ 2019-11-04 16:41 UTC (permalink / raw)
To: QEMU Developers; +Cc: Peter Maydell, Richard Henderson
ping?
http://patchwork.ozlabs.org/patch/1183934/
On Fri, 25 Oct 2019 at 11:08, Christophe Lyon
<christophe.lyon@linaro.org> wrote:
>
> This is derived from cortex-m4 description, adding DP support and FPv5
> instructions with the corresponding flags in isar and mvfr2.
>
> Checked that it could successfully execute
> vrinta.f32 s15, s15
> while cortex-m4 emulation rejects it with "illegal instruction".
>
> Signed-off-by: Christophe Lyon <christophe.lyon@linaro.org>
> ---
> target/arm/cpu.c | 33 +++++++++++++++++++++++++++++++++
> 1 file changed, 33 insertions(+)
>
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index 13813fb..ccae849 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -1954,6 +1954,37 @@ static void cortex_m4_initfn(Object *obj)
> cpu->isar.id_isar6 = 0x00000000;
> }
>
> +static void cortex_m7_initfn(Object *obj)
> +{
> + ARMCPU *cpu = ARM_CPU(obj);
> +
> + set_feature(&cpu->env, ARM_FEATURE_V7);
> + set_feature(&cpu->env, ARM_FEATURE_M);
> + set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
> + set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
> + set_feature(&cpu->env, ARM_FEATURE_VFP4);
> + cpu->midr = 0x411fc272; /* r1p2 */
> + cpu->pmsav7_dregion = 8;
> + cpu->isar.mvfr0 = 0x10110221;
> + cpu->isar.mvfr1 = 0x12000011;
> + cpu->isar.mvfr2 = 0x00000040;
> + cpu->id_pfr0 = 0x00000030;
> + cpu->id_pfr1 = 0x00000200;
> + cpu->id_dfr0 = 0x00100000;
> + cpu->id_afr0 = 0x00000000;
> + cpu->id_mmfr0 = 0x00100030;
> + cpu->id_mmfr1 = 0x00000000;
> + cpu->id_mmfr2 = 0x01000000;
> + cpu->id_mmfr3 = 0x00000000;
> + cpu->isar.id_isar0 = 0x01101110;
> + cpu->isar.id_isar1 = 0x02112000;
> + cpu->isar.id_isar2 = 0x20232231;
> + cpu->isar.id_isar3 = 0x01111131;
> + cpu->isar.id_isar4 = 0x01310132;
> + cpu->isar.id_isar5 = 0x00000000;
> + cpu->isar.id_isar6 = 0x00000000;
> +}
> +
> static void cortex_m33_initfn(Object *obj)
> {
> ARMCPU *cpu = ARM_CPU(obj);
> @@ -2538,6 +2569,8 @@ static const ARMCPUInfo arm_cpus[] = {
> .class_init = arm_v7m_class_init },
> { .name = "cortex-m4", .initfn = cortex_m4_initfn,
> .class_init = arm_v7m_class_init },
> + { .name = "cortex-m7", .initfn = cortex_m7_initfn,
> + .class_init = arm_v7m_class_init },
> { .name = "cortex-m33", .initfn = cortex_m33_initfn,
> .class_init = arm_v7m_class_init },
> { .name = "cortex-r5", .initfn = cortex_r5_initfn },
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/1] target/arm: Add support for cortex-m7 CPU
2019-10-25 9:08 [PATCH 1/1] target/arm: Add support for cortex-m7 CPU Christophe Lyon
2019-11-04 16:41 ` [PING] " Christophe Lyon
@ 2019-11-04 17:08 ` Alex Bennée
2019-11-12 15:18 ` Peter Maydell
2 siblings, 0 replies; 6+ messages in thread
From: Alex Bennée @ 2019-11-04 17:08 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Christophe Lyon, richard.henderson
Christophe Lyon <christophe.lyon@linaro.org> writes:
> This is derived from cortex-m4 description, adding DP support and FPv5
> instructions with the corresponding flags in isar and mvfr2.
>
> Checked that it could successfully execute
> vrinta.f32 s15, s15
> while cortex-m4 emulation rejects it with "illegal instruction".
I couldn't verify the cpu->midr values as most of the sections seem to
be IMPDEF but the rest of the feature bits look OK to me:
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
>
> Signed-off-by: Christophe Lyon <christophe.lyon@linaro.org>
> ---
> target/arm/cpu.c | 33 +++++++++++++++++++++++++++++++++
> 1 file changed, 33 insertions(+)
>
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index 13813fb..ccae849 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -1954,6 +1954,37 @@ static void cortex_m4_initfn(Object *obj)
> cpu->isar.id_isar6 = 0x00000000;
> }
>
> +static void cortex_m7_initfn(Object *obj)
> +{
> + ARMCPU *cpu = ARM_CPU(obj);
> +
> + set_feature(&cpu->env, ARM_FEATURE_V7);
> + set_feature(&cpu->env, ARM_FEATURE_M);
> + set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
> + set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
> + set_feature(&cpu->env, ARM_FEATURE_VFP4);
> + cpu->midr = 0x411fc272; /* r1p2 */
> + cpu->pmsav7_dregion = 8;
> + cpu->isar.mvfr0 = 0x10110221;
> + cpu->isar.mvfr1 = 0x12000011;
> + cpu->isar.mvfr2 = 0x00000040;
> + cpu->id_pfr0 = 0x00000030;
> + cpu->id_pfr1 = 0x00000200;
> + cpu->id_dfr0 = 0x00100000;
> + cpu->id_afr0 = 0x00000000;
> + cpu->id_mmfr0 = 0x00100030;
> + cpu->id_mmfr1 = 0x00000000;
> + cpu->id_mmfr2 = 0x01000000;
> + cpu->id_mmfr3 = 0x00000000;
> + cpu->isar.id_isar0 = 0x01101110;
> + cpu->isar.id_isar1 = 0x02112000;
> + cpu->isar.id_isar2 = 0x20232231;
> + cpu->isar.id_isar3 = 0x01111131;
> + cpu->isar.id_isar4 = 0x01310132;
> + cpu->isar.id_isar5 = 0x00000000;
> + cpu->isar.id_isar6 = 0x00000000;
> +}
> +
> static void cortex_m33_initfn(Object *obj)
> {
> ARMCPU *cpu = ARM_CPU(obj);
> @@ -2538,6 +2569,8 @@ static const ARMCPUInfo arm_cpus[] = {
> .class_init = arm_v7m_class_init },
> { .name = "cortex-m4", .initfn = cortex_m4_initfn,
> .class_init = arm_v7m_class_init },
> + { .name = "cortex-m7", .initfn = cortex_m7_initfn,
> + .class_init = arm_v7m_class_init },
> { .name = "cortex-m33", .initfn = cortex_m33_initfn,
> .class_init = arm_v7m_class_init },
> { .name = "cortex-r5", .initfn = cortex_r5_initfn },
--
Alex Bennée
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PING] [PATCH 1/1] target/arm: Add support for cortex-m7 CPU
2019-11-04 16:41 ` [PING] " Christophe Lyon
@ 2019-11-05 20:23 ` Peter Maydell
2019-11-05 20:25 ` Christophe Lyon
0 siblings, 1 reply; 6+ messages in thread
From: Peter Maydell @ 2019-11-05 20:23 UTC (permalink / raw)
To: Christophe Lyon; +Cc: Richard Henderson, QEMU Developers
On Mon, 4 Nov 2019 at 16:41, Christophe Lyon <christophe.lyon@linaro.org> wrote:
>
> ping?
This is on my list to review, but it's missed softfreeze so
as a new feature it will go into 5.0 once trunk reopens for
development at the end of the year, so it's not the
highest priority for patch review for me I'm afraid.
thanks
-- PMM
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PING] [PATCH 1/1] target/arm: Add support for cortex-m7 CPU
2019-11-05 20:23 ` Peter Maydell
@ 2019-11-05 20:25 ` Christophe Lyon
0 siblings, 0 replies; 6+ messages in thread
From: Christophe Lyon @ 2019-11-05 20:25 UTC (permalink / raw)
To: Peter Maydell; +Cc: Richard Henderson, QEMU Developers
On Tue, 5 Nov 2019 at 21:23, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> On Mon, 4 Nov 2019 at 16:41, Christophe Lyon <christophe.lyon@linaro.org> wrote:
> >
> > ping?
>
> This is on my list to review, but it's missed softfreeze so
> as a new feature it will go into 5.0 once trunk reopens for
> development at the end of the year, so it's not the
> highest priority for patch review for me I'm afraid.
>
OK, I hoped it was still in time for softfreeze :-(
Thanks for the clarification.
> thanks
> -- PMM
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/1] target/arm: Add support for cortex-m7 CPU
2019-10-25 9:08 [PATCH 1/1] target/arm: Add support for cortex-m7 CPU Christophe Lyon
2019-11-04 16:41 ` [PING] " Christophe Lyon
2019-11-04 17:08 ` Alex Bennée
@ 2019-11-12 15:18 ` Peter Maydell
2 siblings, 0 replies; 6+ messages in thread
From: Peter Maydell @ 2019-11-12 15:18 UTC (permalink / raw)
To: Christophe Lyon; +Cc: Richard Henderson, QEMU Developers
On Fri, 25 Oct 2019 at 10:08, Christophe Lyon
<christophe.lyon@linaro.org> wrote:
>
> This is derived from cortex-m4 description, adding DP support and FPv5
> instructions with the corresponding flags in isar and mvfr2.
>
> Checked that it could successfully execute
> vrinta.f32 s15, s15
> while cortex-m4 emulation rejects it with "illegal instruction".
>
> Signed-off-by: Christophe Lyon <christophe.lyon@linaro.org>
> ---
> target/arm/cpu.c | 33 +++++++++++++++++++++++++++++++++
> 1 file changed, 33 insertions(+)
>
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index 13813fb..ccae849 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -1954,6 +1954,37 @@ static void cortex_m4_initfn(Object *obj)
> cpu->isar.id_isar6 = 0x00000000;
> }
>
> +static void cortex_m7_initfn(Object *obj)
> +{
> + ARMCPU *cpu = ARM_CPU(obj);
> +
> + set_feature(&cpu->env, ARM_FEATURE_V7);
> + set_feature(&cpu->env, ARM_FEATURE_M);
> + set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
> + set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
> + set_feature(&cpu->env, ARM_FEATURE_VFP4);
> + cpu->midr = 0x411fc272; /* r1p2 */
> + cpu->pmsav7_dregion = 8;
> + cpu->isar.mvfr0 = 0x10110221;
> + cpu->isar.mvfr1 = 0x12000011;
> + cpu->isar.mvfr2 = 0x00000040;
> + cpu->id_pfr0 = 0x00000030;
> + cpu->id_pfr1 = 0x00000200;
> + cpu->id_dfr0 = 0x00100000;
> + cpu->id_afr0 = 0x00000000;
> + cpu->id_mmfr0 = 0x00100030;
> + cpu->id_mmfr1 = 0x00000000;
> + cpu->id_mmfr2 = 0x01000000;
> + cpu->id_mmfr3 = 0x00000000;
> + cpu->isar.id_isar0 = 0x01101110;
> + cpu->isar.id_isar1 = 0x02112000;
> + cpu->isar.id_isar2 = 0x20232231;
> + cpu->isar.id_isar3 = 0x01111131;
> + cpu->isar.id_isar4 = 0x01310132;
> + cpu->isar.id_isar5 = 0x00000000;
> + cpu->isar.id_isar6 = 0x00000000;
> +}
> +
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
I've put this in my list of patches to queue for 5.0.
thanks
-- PMM
^ permalink raw reply [flat|nested] 6+ messages in thread
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2019-10-25 9:08 [PATCH 1/1] target/arm: Add support for cortex-m7 CPU Christophe Lyon
2019-11-04 16:41 ` [PING] " Christophe Lyon
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2019-11-05 20:25 ` Christophe Lyon
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