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X-Received-From: 2a00:1450:4864:20::344 Subject: Re: [Qemu-devel] [PATCH for-4.2 18/24] target/arm: Update arm_sctlr for VHE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, beata.michalska@linaro.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Richard Henderson writes: > Use this function in many more places in order to select > the correct control. > > Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e > --- > target/arm/cpu.h | 10 ++++++---- > target/arm/arch_dump.c | 2 +- > target/arm/helper-a64.c | 2 +- > target/arm/helper.c | 10 +++++----- > target/arm/pauth_helper.c | 9 +-------- > 5 files changed, 14 insertions(+), 19 deletions(-) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 7310adfd9b..7efbb488d9 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -3104,11 +3104,13 @@ static inline bool arm_sctlr_b(CPUARMState *env) > static inline uint64_t arm_sctlr(CPUARMState *env, int el) > { > if (el =3D=3D 0) { > - /* FIXME: ARMv8.1-VHE S2 translation regime. */ > - return env->cp15.sctlr_el[1]; > - } else { > - return env->cp15.sctlr_el[el]; > + if (arm_el_is_aa64(env, 2) && (arm_hcr_el2_eff(env) & HCR_E2H)) { > + el =3D 2; > + } else { > + el =3D 1; > + } > } > + return env->cp15.sctlr_el[el]; > } > > > diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c > index 26a2c09868..5fbd008d8c 100644 > --- a/target/arm/arch_dump.c > +++ b/target/arm/arch_dump.c > @@ -320,7 +320,7 @@ int cpu_get_dump_info(ArchDumpInfo *info, > * dump a hypervisor that happens to be running an opposite-endian > * kernel. > */ > - info->d_endian =3D (env->cp15.sctlr_el[1] & SCTLR_EE) !=3D 0 > + info->d_endian =3D (arm_sctlr(env, 1) & SCTLR_EE) !=3D 0 > ? ELFDATA2MSB : ELFDATA2LSB; > > return 0; > diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c > index 060699b901..3bf1b731e7 100644 > --- a/target/arm/helper-a64.c > +++ b/target/arm/helper-a64.c > @@ -70,7 +70,7 @@ static void daif_check(CPUARMState *env, uint32_t op, > uint32_t imm, uintptr_t ra) > { > /* DAIF update to PSTATE. This is OK from EL0 only if UMA is set. */ > - if (arm_current_el(env) =3D=3D 0 && !(env->cp15.sctlr_el[1] & SCTLR_= UMA)) { > + if (arm_current_el(env) =3D=3D 0 && !(arm_sctlr(env, 0) & SCTLR_UMA)= ) { > raise_exception_ra(env, EXCP_UDEF, > syn_aa64_sysregtrap(0, extract32(op, 0, 3), > extract32(op, 3, 3), 4, > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 54c328b844..db13a8f9c0 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -3868,7 +3868,7 @@ static void aa64_fpsr_write(CPUARMState *env, const= ARMCPRegInfo *ri, > static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegI= nfo *ri, > bool isread) > { > - if (arm_current_el(env) =3D=3D 0 && !(env->cp15.sctlr_el[1] & SCTLR_= UMA)) { > + if (arm_current_el(env) =3D=3D 0 && !(arm_sctlr(env, 0) & SCTLR_UMA)= ) { > return CP_ACCESS_TRAP; > } > return CP_ACCESS_OK; > @@ -3887,7 +3887,7 @@ static CPAccessResult aa64_cacheop_access(CPUARMSta= te *env, > /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless > * SCTLR_EL1.UCI is set. > */ > - if (arm_current_el(env) =3D=3D 0 && !(env->cp15.sctlr_el[1] & SCTLR_= UCI)) { > + if (arm_current_el(env) =3D=3D 0 && !(arm_sctlr(env, 0) & SCTLR_UCI)= ) { > return CP_ACCESS_TRAP; > } > return CP_ACCESS_OK; > @@ -4114,7 +4114,7 @@ static CPAccessResult aa64_zva_access(CPUARMState *= env, const ARMCPRegInfo *ri, > /* We don't implement EL2, so the only control on DC ZVA is the > * bit in the SCTLR which can prohibit access for EL0. > */ > - if (arm_current_el(env) =3D=3D 0 && !(env->cp15.sctlr_el[1] & SCTLR_= DZE)) { > + if (arm_current_el(env) =3D=3D 0 && !(arm_sctlr(env, 0) & SCTLR_DZE)= ) { > return CP_ACCESS_TRAP; > } > return CP_ACCESS_OK; > @@ -5344,7 +5344,7 @@ static CPAccessResult ctr_el0_access(CPUARMState *e= nv, const ARMCPRegInfo *ri, > /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64, > * but the AArch32 CTR has its own reginfo struct) > */ > - if (arm_current_el(env) =3D=3D 0 && !(env->cp15.sctlr_el[1] & SCTLR_= UCT)) { > + if (arm_current_el(env) =3D=3D 0 && !(arm_sctlr(env, 0) & SCTLR_UCT)= ) { > return CP_ACCESS_TRAP; > } > return CP_ACCESS_OK; > @@ -8161,7 +8161,7 @@ static void take_aarch32_exception(CPUARMState *env= , int new_mode, > env->uncached_cpsr =3D (env->uncached_cpsr & ~CPSR_M) | new_mode; > /* Set new mode endianness */ > env->uncached_cpsr &=3D ~CPSR_E; > - if (env->cp15.sctlr_el[arm_current_el(env)] & SCTLR_EE) { > + if (arm_sctlr(env, arm_current_el(env)) & SCTLR_EE) { > env->uncached_cpsr |=3D CPSR_E; > } > /* J and IL must always be cleared for exception entry */ > diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c > index d3194f2043..42c9141bb7 100644 > --- a/target/arm/pauth_helper.c > +++ b/target/arm/pauth_helper.c > @@ -386,14 +386,7 @@ static void pauth_check_trap(CPUARMState *env, int e= l, uintptr_t ra) > > static bool pauth_key_enabled(CPUARMState *env, int el, uint32_t bit) > { > - uint32_t sctlr; > - if (el =3D=3D 0) { > - /* FIXME: ARMv8.1-VHE S2 translation regime. */ > - sctlr =3D env->cp15.sctlr_el[1]; > - } else { > - sctlr =3D env->cp15.sctlr_el[el]; > - } > - return (sctlr & bit) !=3D 0; > + return (arm_sctlr(env, el) & bit) !=3D 0; > } > > uint64_t HELPER(pacia)(CPUARMState *env, uint64_t x, uint64_t y) -- Alex Benn=C3=A9e