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X-Received-From: 2a00:1450:4864:20::343 Subject: Re: [Qemu-devel] [PATCH for-4.2 16/24] target/arm: Add regime_has_2_ranges X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, beata.michalska@linaro.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Richard Henderson writes: Can you elucidate what we mean by having 2 ranges? > Signed-off-by: Richard Henderson > --- > target/arm/internals.h | 16 ++++++++++++++++ > target/arm/helper.c | 22 +++++----------------- > target/arm/translate-a64.c | 3 +-- > 3 files changed, 22 insertions(+), 19 deletions(-) > > diff --git a/target/arm/internals.h b/target/arm/internals.h > index 047cbfd1d7..f653e0e7f5 100644 > --- a/target/arm/internals.h > +++ b/target/arm/internals.h > @@ -824,6 +824,22 @@ static inline void arm_call_el_change_hook(ARMCPU *c= pu) > } > } > > +/* Return true if this address translation regime has two ranges. */ > +static inline bool regime_has_2_ranges(ARMMMUIdx mmu_idx) > +{ > + switch (mmu_idx) { > + case ARMMMUIdx_Stage1_E0: > + case ARMMMUIdx_Stage1_E1: > + case ARMMMUIdx_EL10_0: > + case ARMMMUIdx_EL10_1: > + case ARMMMUIdx_EL20_0: > + case ARMMMUIdx_EL20_2: > + return true; > + default: > + return false; > + } > +} > + > /* Return true if this address translation regime is secure */ > static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) > { > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 240a6ed168..2d5658f9e3 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -8999,15 +8999,8 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx = mmu_idx, bool is_aa64, > } > > if (is_aa64) { > - switch (regime_el(env, mmu_idx)) { > - case 1: > - if (!is_user) { > - xn =3D pxn || (user_rw & PAGE_WRITE); > - } > - break; > - case 2: > - case 3: > - break; > + if (regime_has_2_ranges(mmu_idx) && !is_user) { > + xn =3D pxn || (user_rw & PAGE_WRITE); > } > } else if (arm_feature(env, ARM_FEATURE_V7)) { > switch (regime_el(env, mmu_idx)) { > @@ -9541,7 +9534,6 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState= *env, uint64_t va, > ARMMMUIdx mmu_idx) > { > uint64_t tcr =3D regime_tcr(env, mmu_idx)->raw_tcr; > - uint32_t el =3D regime_el(env, mmu_idx); > bool tbi, tbid, epd, hpd, using16k, using64k; > int select, tsz; > > @@ -9551,7 +9543,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState= *env, uint64_t va, > */ > select =3D extract64(va, 55, 1); > > - if (el > 1) { > + if (!regime_has_2_ranges(mmu_idx)) { > tsz =3D extract32(tcr, 0, 6); > using64k =3D extract32(tcr, 14, 1); > using16k =3D extract32(tcr, 15, 1); > @@ -9707,10 +9699,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, t= arget_ulong address, > param =3D aa64_va_parameters(env, address, mmu_idx, > access_type !=3D MMU_INST_FETCH); > level =3D 0; > - /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mar= k it > - * invalid. > - */ > - ttbr1_valid =3D (el < 2); > + ttbr1_valid =3D regime_has_2_ranges(mmu_idx); > addrsize =3D 64 - 8 * param.tbi; > inputsize =3D 64 - param.tsz; > } else { > @@ -11361,8 +11350,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, targe= t_ulong *pc, > ARMVAParameters p0 =3D aa64_va_parameters_both(env, 0, stage= 1); > int tbii, tbid; > > - /* FIXME: ARMv8.1-VHE S2 translation regime. */ > - if (regime_el(env, stage1) < 2) { > + if (regime_has_2_ranges(mmu_idx)) { > ARMVAParameters p1 =3D aa64_va_parameters_both(env, -1, = stage1); > tbid =3D (p1.tbi << 1) | p0.tbi; > tbii =3D tbid & ~((p1.tbid << 1) | p0.tbid); > diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c > index a9e65fe347..5679349310 100644 > --- a/target/arm/translate-a64.c > +++ b/target/arm/translate-a64.c > @@ -176,8 +176,7 @@ static void gen_top_byte_ignore(DisasContext *s, TCGv= _i64 dst, > if (tbi =3D=3D 0) { > /* Load unmodified address */ > tcg_gen_mov_i64(dst, src); > - } else if (s->current_el >=3D 2) { > - /* FIXME: ARMv8.1-VHE S2 translation regime. */ > + } else if (!regime_has_2_ranges(s->mmu_idx)) { > /* Force tag byte to all zero */ > tcg_gen_extract_i64(dst, src, 0, 56); > } else { -- Alex Benn=C3=A9e