From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57807) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aWTBG-0003ME-AF for qemu-devel@nongnu.org; Thu, 18 Feb 2016 13:19:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aWTBD-0004J1-4f for qemu-devel@nongnu.org; Thu, 18 Feb 2016 13:19:58 -0500 Received: from mail-wm0-x231.google.com ([2a00:1450:400c:c09::231]:34597) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aWTBC-0004Ih-MX for qemu-devel@nongnu.org; Thu, 18 Feb 2016 13:19:55 -0500 Received: by mail-wm0-x231.google.com with SMTP id b205so37158671wmb.1 for ; Thu, 18 Feb 2016 10:19:54 -0800 (PST) References: <1454059965-23402-1-git-send-email-a.rigo@virtualopensystems.com> <1454059965-23402-16-git-send-email-a.rigo@virtualopensystems.com> From: Alex =?utf-8?Q?Benn=C3=A9e?= In-reply-to: <1454059965-23402-16-git-send-email-a.rigo@virtualopensystems.com> Date: Thu, 18 Feb 2016 18:19:52 +0000 Message-ID: <87wpq1dgon.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [RFC v7 15/16] target-arm: cpu64: use custom set_excl hook List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alvise Rigo Cc: mttcg@listserver.greensocs.com, claudio.fontana@huawei.com, qemu-devel@nongnu.org, pbonzini@redhat.com, jani.kokkonen@huawei.com, tech@virtualopensystems.com, rth@twiddle.net Alvise Rigo writes: > In aarch64 the LDXP/STXP instructions allow to perform up to 128 bits > exclusive accesses. However, due to a softmmu limitation, such wide > accesses are not allowed. > > To workaround this limitation, we need to support LoadLink instructions > that cover at least 128 consecutive bits (see the next patch for more > details). > > Suggested-by: Jani Kokkonen > Suggested-by: Claudio Fontana > Signed-off-by: Alvise Rigo Reviewed-by: Alex Bennée > --- > target-arm/cpu64.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c > index cc177bb..1d45e66 100644 > --- a/target-arm/cpu64.c > +++ b/target-arm/cpu64.c > @@ -287,6 +287,13 @@ static void aarch64_cpu_set_pc(CPUState *cs, vaddr value) > } > } > > +static void aarch64_set_excl_range(CPUState *cpu, hwaddr addr, hwaddr size) > +{ > + cpu->excl_protected_range.begin = addr; > + /* At least cover 128 bits for a STXP access (two paired doublewords case)*/ > + cpu->excl_protected_range.end = addr + 16; > +} > + > static void aarch64_cpu_class_init(ObjectClass *oc, void *data) > { > CPUClass *cc = CPU_CLASS(oc); > @@ -297,6 +304,7 @@ static void aarch64_cpu_class_init(ObjectClass *oc, void *data) > cc->gdb_write_register = aarch64_cpu_gdb_write_register; > cc->gdb_num_core_regs = 34; > cc->gdb_core_xml_file = "aarch64-core.xml"; > + cc->cpu_set_excl_protected_range = aarch64_set_excl_range; > } > > static void aarch64_cpu_register(const ARMCPUInfo *info) -- Alex Bennée