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[88.21.203.248]) by smtp.gmail.com with ESMTPSA id w83sm8601146wmb.37.2020.05.07.07.08.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 07 May 2020 07:08:13 -0700 (PDT) Subject: Re: [PATCH] target/arm: Use correct GDB XML for M-profile cores To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20200507134755.13997-1-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <88812e26-b6a7-8f80-f9d1-cb51ed5721c9@amsat.org> Date: Thu, 7 May 2020 16:08:12 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.5.0 MIME-Version: 1.0 In-Reply-To: <20200507134755.13997-1-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::344; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x344.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 5/7/20 3:47 PM, Peter Maydell wrote: > GDB's remote protocol requires M-profile cores to use the feature > name 'org.gnu.gdb.arm.m-profile' instead of the 'org.gnu.gdb.arm.core' > feature used for A- and R-profile cores. We weren't doing this, which > meant GDB treated our M-profile cores like A-profile ones. This mostly > doesn't matter, but for instance means that it doesn't correctly > handle backtraces where an M-profile exception frame is involved. > > Ship a copy of GDB's arm-m-profile.xml and use it on the M-profile > cores. The integer registers have the same offsets as the > arm-core.xml, but register 25 is the M-profile XPSR rather than the > A-profile CPSR, so we need to update arm_cpu_gdb_read_register() and > arm_cpu_gdb_write_register() to handle XSPR reads and writes. > > Fixes: https://bugs.launchpad.net/qemu/+bug/1877136 > Signed-off-by: Peter Maydell > --- > configure | 4 ++-- > target/arm/cpu.c | 1 + > target/arm/gdbstub.c | 22 ++++++++++++++++++---- > gdb-xml/arm-m-profile.xml | 27 +++++++++++++++++++++++++++ > 4 files changed, 48 insertions(+), 6 deletions(-) > create mode 100644 gdb-xml/arm-m-profile.xml > > diff --git a/configure b/configure > index 0d69c360c0e..360e7e6a0a4 100755 > --- a/configure > +++ b/configure > @@ -7806,14 +7806,14 @@ case "$target_name" in > TARGET_SYSTBL_ABI=common,oabi > bflt="yes" > mttcg="yes" > - gdb_xml_files="arm-core.xml arm-vfp.xml arm-vfp3.xml arm-neon.xml" > + gdb_xml_files="arm-core.xml arm-vfp.xml arm-vfp3.xml arm-neon.xml arm-m-profile.xml" > ;; > aarch64|aarch64_be) > TARGET_ARCH=aarch64 > TARGET_BASE_ARCH=arm > bflt="yes" > mttcg="yes" > - gdb_xml_files="aarch64-core.xml aarch64-fpu.xml arm-core.xml arm-vfp.xml arm-vfp3.xml arm-neon.xml" > + gdb_xml_files="aarch64-core.xml aarch64-fpu.xml arm-core.xml arm-vfp.xml arm-vfp3.xml arm-neon.xml arm-m-profile.xml" > ;; > cris) > ;; > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index 5d64adfe76e..b386bbbfd12 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -2179,6 +2179,7 @@ static void arm_v7m_class_init(ObjectClass *oc, void *data) > #endif > > cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; > + cc->gdb_core_xml_file = "arm-m-profile.xml"; > } > > static const ARMCPRegInfo cortexr5_cp_reginfo[] = { > diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c > index 063551df234..ecfa88f8e60 100644 > --- a/target/arm/gdbstub.c > +++ b/target/arm/gdbstub.c > @@ -57,8 +57,12 @@ int arm_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) > } > return gdb_get_reg32(mem_buf, 0); > case 25: > - /* CPSR */ > - return gdb_get_reg32(mem_buf, cpsr_read(env)); > + /* CPSR, or XPSR for M-profile */ > + if (arm_feature(env, ARM_FEATURE_M)) { > + return gdb_get_reg32(mem_buf, xpsr_read(env)); > + } else { > + return gdb_get_reg32(mem_buf, cpsr_read(env)); > + } > } > /* Unknown register. */ > return 0; > @@ -98,8 +102,18 @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) > } > return 4; > case 25: > - /* CPSR */ > - cpsr_write(env, tmp, 0xffffffff, CPSRWriteByGDBStub); > + /* CPSR, or XPSR for M-profile */ > + if (arm_feature(env, ARM_FEATURE_M)) { > + /* > + * Don't allow writing to XPSR.Exception as it can cause > + * a transition into or out of handler mode (it's not > + * writeable via the MSR insn so this is a reasonable > + * restriction). Other fields are safe to update. > + */ > + xpsr_write(env, tmp, ~XPSR_EXCP); > + } else { > + cpsr_write(env, tmp, 0xffffffff, CPSRWriteByGDBStub); > + } > return 4; > } > /* Unknown register. */ > diff --git a/gdb-xml/arm-m-profile.xml b/gdb-xml/arm-m-profile.xml > new file mode 100644 > index 00000000000..5319d764eeb > --- /dev/null > +++ b/gdb-xml/arm-m-profile.xml > @@ -0,0 +1,27 @@ > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > Reviewed-by: Philippe Mathieu-Daudé