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[189.204.200.163]) by smtp.gmail.com with ESMTPSA id 189sm2248194qkh.99.2021.05.13.04.36.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 13 May 2021 04:36:25 -0700 (PDT) Subject: Re: [PATCH v4 30/31] target/ppc: Implement vcfuged instruction To: matheus.ferst@eldorado.org.br, qemu-devel@nongnu.org, qemu-ppc@nongnu.org References: <20210512185441.3619828-1-matheus.ferst@eldorado.org.br> <20210512185441.3619828-31-matheus.ferst@eldorado.org.br> From: Richard Henderson Message-ID: <89dbecb1-085a-4d94-9d6d-6e193fde9fd7@linaro.org> Date: Thu, 13 May 2021 06:36:22 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.8.1 MIME-Version: 1.0 In-Reply-To: <20210512185441.3619828-31-matheus.ferst@eldorado.org.br> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::f29; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf29.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lagarcia@br.ibm.com, bruno.larsen@eldorado.org.br, luis.pires@eldorado.org.br, f4bug@amsat.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 5/12/21 1:54 PM, matheus.ferst@eldorado.org.br wrote: > From: Matheus Ferst > > Signed-off-by: Matheus Ferst > --- > target/ppc/insn32.decode | 7 ++++ > target/ppc/translate.c | 1 + > target/ppc/translate/vector-impl.c.inc | 50 ++++++++++++++++++++++++++ > 3 files changed, 58 insertions(+) > create mode 100644 target/ppc/translate/vector-impl.c.inc > > diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode > index 64788e2a4b..73b5ea0422 100644 > --- a/target/ppc/insn32.decode > +++ b/target/ppc/insn32.decode > @@ -23,6 +23,9 @@ > %ds_si 2:s14 !function=times_4 > @DS ...... rt:5 ra:5 .............. .. &D si=%ds_si > > +&VX vrt vra vrb > +@VX ...... vrt:5 vra:5 vrb:5 .......... . &VX > + > &X rt ra rb > @X ...... rt:5 ra:5 rb:5 .......... . &X > > @@ -97,3 +100,7 @@ SETBC 011111 ..... ..... ----- 0110000000 - @X_bi > SETBCR 011111 ..... ..... ----- 0110100000 - @X_bi > SETNBC 011111 ..... ..... ----- 0111000000 - @X_bi > SETNBCR 011111 ..... ..... ----- 0111100000 - @X_bi > + > +## Vector Bit Manipulation Instruction > + > +VCFUGED 000100 ..... ..... ..... 10101001101 @VX > diff --git a/target/ppc/translate.c b/target/ppc/translate.c > index 477e3deede..847de8e012 100644 > --- a/target/ppc/translate.c > +++ b/target/ppc/translate.c > @@ -7627,6 +7627,7 @@ static int times_4(DisasContext *ctx, int x) > #include "translate/vmx-impl.c.inc" > > #include "translate/vsx-impl.c.inc" > +#include "translate/vector-impl.c.inc" > > #include "translate/dfp-impl.c.inc" > > diff --git a/target/ppc/translate/vector-impl.c.inc b/target/ppc/translate/vector-impl.c.inc > new file mode 100644 > index 0000000000..4e07de5671 > --- /dev/null > +++ b/target/ppc/translate/vector-impl.c.inc > @@ -0,0 +1,50 @@ > +/* > + * Power ISA decode for Vector Facility instructions > + * > + * Copyright (c) 2021 Matheus Ferst > + * > + * This library is free software; you can redistribute it and/or > + * modify it under the terms of the GNU Lesser General Public > + * License as published by the Free Software Foundation; either > + * version 2.1 of the License, or (at your option) any later version. > + * > + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + * Lesser General Public License for more details. > + * > + * You should have received a copy of the GNU Lesser General Public > + * License along with this library; if not, see . > + */ > + > +static bool trans_VCFUGED(DisasContext *ctx, arg_VX *a) > +{ > + TCGv_i64 tgt, src, mask; > + > + if (unlikely(!ctx->altivec_enabled)) { > + gen_exception(ctx, POWERPC_EXCP_VPU); > + return true; > + } You have to REQUIRE_INSN_FLAGS(something) before checking for altivec_enabled. You're going to want to create some boilerplate for this, because it's going to get repeated a *lot*. > + // centrifuge lower double word > + get_cpu_vsrl(src, a->vra+32); > + get_cpu_vsrl(mask, a->vrb+32); > + gen_helper_cfuged(tgt, src, mask); > + set_cpu_vsrl(a->vrt+32, tgt); > + > + // centrifuge higher double word > + get_cpu_vsrh(src, a->vra+32); > + get_cpu_vsrh(mask, a->vrb+32); > + gen_helper_cfuged(tgt, src, mask); > + set_cpu_vsrh(a->vrt+32, tgt); This has multiple checkpatch errors. r~