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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id a188sm1282543pfb.108.2021.01.15.08.40.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 15 Jan 2021 08:40:03 -0800 (PST) Subject: Re: [PATCH] util/cacheflush: Fix error generated by clang To: Gan Qixin , qemu-devel@nongnu.org, qemu-trivial@nongnu.org References: <20210115075656.717957-1-ganqixin@huawei.com> From: Richard Henderson Message-ID: <8d1971bb-0c0d-b7cb-5fed-4d105e17a511@linaro.org> Date: Fri, 15 Jan 2021 06:39:59 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20210115075656.717957-1-ganqixin@huawei.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kuhn.chenqun@huawei.com, Paolo Bonzini , zhang.zhanghailiang@huawei.com, Euler Robot Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 1/14/21 9:56 PM, Gan Qixin wrote: > When compiling qemu-fuzz-i386 on aarch64 host, clang reported the following > error: > > ../util/cacheflush.c:38:44: error: value size does not match register size > specified by the constraint and modifier [-Werror,-Wasm-operand-widths] > asm volatile("mrs\t%0, ctr_el0" : "=r"(save_ctr_el0)); > ^ > ../util/cacheflush.c:38:24: note: use constraint modifier "w" > asm volatile("mrs\t%0, ctr_el0" : "=r"(save_ctr_el0)); > ^~ > %w0 > > Modify the type of save_ctr_el0 to uint64_t to fix it. > > Reported-by: Euler Robot > Signed-off-by: Gan Qixin > --- > Cc: Richard Henderson > Cc: Paolo Bonzini > --- > util/cacheflush.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) This is clang being overly-picky. IMO it should have done the mrs into a 64-bit register, then truncated the value when storing to the 32-bit variable. Which is what GCC does. Certainly the code as written only needs the low 20 bits of the result. But your change will not really make any difference to the generated code, except for 4 more bytes of storage, so: Reviewed-by: Richard Henderson r~