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[204.210.126.223]) by smtp.gmail.com with ESMTPSA id v7sm17673200pjk.37.2021.07.21.15.33.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 21 Jul 2021 15:33:43 -0700 (PDT) Subject: Re: [PATCH for-6.2 31/34] target/arm: Implement MVE VCTP To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20210713133726.26842-1-peter.maydell@linaro.org> <20210713133726.26842-32-peter.maydell@linaro.org> From: Richard Henderson Message-ID: <8f65e081-e173-d841-c145-c8db03e72c28@linaro.org> Date: Wed, 21 Jul 2021 12:33:40 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <20210713133726.26842-32-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.117, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 7/13/21 3:37 AM, Peter Maydell wrote: > Implement the MVE VCTP insn, which sets the VPR.P0 predicate bits so > as to predicate any element at index Rn or greater is predicated. As > with VPNOT, this insn itself is predicable and subject to beatwise > execution. > > The calculation of the mask is the same as is used to determine > ltpmask in mve_element_mask(), but we precalculate masklen in > generated code to avoid having to have 4 helpers specialized by size. > > We put the decode line in with the low-overhead-loop insns in > t32.decode because it's logically part of that collection of insn > patterns, even though it is an MVE only insn. > > Signed-off-by: Peter Maydell > --- > target/arm/helper-mve.h | 2 ++ > target/arm/translate-a32.h | 1 + > target/arm/t32.decode | 1 + > target/arm/mve_helper.c | 20 ++++++++++++++++++++ > target/arm/translate-mve.c | 2 +- > target/arm/translate.c | 33 +++++++++++++++++++++++++++++++++ > 6 files changed, 58 insertions(+), 1 deletion(-) Reviewed-by: Richard Henderson r~