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12 Apr 2021 19:21:35 -0700 IronPort-SDR: Jf+nuujwPxdHBhrE+j2hmFQJM9v8fN/wL1FP4gTbOvd5R8yEGpENIODXkzUz97fqfZppyQKG74 CRhRUyxlWB1gfL6wph2yt48Jbl96JxIEiRAGs7pxjSAKrFjS2hP387jC55MM5E2XWs4gUM7u3w VdKV3v2qeWVQpDtsLGSlabIgz/WBf16v9bhO5+XiDksVq2vYSxsguBWPICa9y8q+XzNBzuh1QM VlKnBfkDuQG925+02l8YaNTJVDZy5WPLVawnykWu8Ktu51IwsUhapSQxSuq19kmdcMKk2xkDt0 kuk= WDCIronportException: Internal Received: from unknown (HELO alistair-risc6-laptop.wdc.com) ([10.225.165.16]) by uls-op-cesaip01.wdc.com with ESMTP; 12 Apr 2021 19:42:05 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 2/8] target/riscv: Define ePMP mseccfg Date: Tue, 13 Apr 2021 12:41:55 +1000 Message-Id: <919a4f45cbfd039545efadd4cfb0cd9ada8cfdb9.1618281655.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=730c0c5bd=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Hou Weiying Use address 0x390 and 0x391 for the ePMP CSRs. Signed-off-by: Hongzheng-Li Signed-off-by: Hou Weiying Signed-off-by: Myriad-Dreamin Reviewed-by: Alistair Francis Message-Id: [ Changes by AF: - Tidy up commit message ] Signed-off-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/cpu_bits.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 8549d77b4f..24d89939a0 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -220,6 +220,9 @@ #define CSR_MTINST 0x34a #define CSR_MTVAL2 0x34b +/* Enhanced Physical Memory Protection (ePMP) */ +#define CSR_MSECCFG 0x390 +#define CSR_MSECCFGH 0x391 /* Physical Memory Protection */ #define CSR_PMPCFG0 0x3a0 #define CSR_PMPCFG1 0x3a1 -- 2.31.1