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[88.26.246.243]) by smtp.gmail.com with ESMTPSA id r2sm16556080wma.1.2019.10.11.08.32.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 11 Oct 2019 08:32:27 -0700 (PDT) Subject: Re: [PATCH v30 0/8] QEMU AVR 8 bit cores To: Michael Rolnik , qemu-devel@nongnu.org References: <20190902140134.74081-1-mrolnik@gmail.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <949009b8-58ec-4a9e-cfd7-7d4611fad380@redhat.com> Date: Fri, 11 Oct 2019 17:32:26 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.1.0 MIME-Version: 1.0 In-Reply-To: <20190902140134.74081-1-mrolnik@gmail.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dovgaluk@ispras.ru, thuth@redhat.com, richard.henderson@linaro.org, imammedo@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Hi Michael, On 9/2/19 4:01 PM, Michael Rolnik wrote: > This series of patches adds 8bit AVR cores to QEMU. > All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully tested yet. > However I was able to execute simple code with functions. e.g fibonacci calculation. > This series of patches include a non real, sample board. > No fuses support yet. PC is set to 0 at reset. > > the patches include the following > 1. just a basic 8bit AVR CPU, without instruction decoding or translation > 2. CPU features which allow define the following 8bit AVR cores > avr1 > avr2 avr25 > avr3 avr31 avr35 > avr4 > avr5 avr51 > avr6 > xmega2 xmega4 xmega5 xmega6 xmega7 > 3. a definition of sample machine with SRAM, FLASH and CPU which allows to execute simple code > 4. encoding for all AVR instructions > 5. interrupt handling > 6. helpers for IN, OUT, SLEEP, WBR & unsupported instructions > 7. a decoder which given an opcode decides what istruction it is > 8. translation of AVR instruction into TCG > 9. all features together > [..] > Michael Rolnik (7): > target/avr: Add outward facing interfaces and core CPU logic > target/avr: Add instruction helpers > target/avr: Add instruction decoding > target/avr: Add instruction translation > target/avr: Add example board configuration > target/avr: Register AVR support with the rest of QEMU, the build > system, and the MAINTAINERS file > target/avr: Add tests > > Sarah Harris (1): > target/avr: Add limited support for USART and 16 bit timer peripherals Overall architecture patches look good, but I'd like some more time to review the hardware patches. Unfortunately I won't have time until November. There was a chat on IRC about your series, I suggested Richard we could merge patches 1-4 and 7. They are almost sufficient to run the qemu-avr-tests gdbstub tests (but not the FreeRTOS ones). Regards, Phil.