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19 Sep 2019 15:29:09 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v1 3/6] riscv/sifive_u: Manually define the machine Date: Thu, 19 Sep 2019 15:25:01 -0700 Message-Id: <95b47a08da3038df82cd1cc9d69cd005270906f8.1568931866.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x X-Received-From: 68.232.143.124 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Instead of using the DEFINE_MACHINE() macro to define the machine let's do it manually. This allows us to specify machine properties. This patch is no functional change. Signed-off-by: Alistair Francis --- hw/riscv/sifive_u.c | 27 +++++++++++++++++++++++---- include/hw/riscv/sifive_u.h | 7 ++++++- 2 files changed, 29 insertions(+), 5 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 9c5d791320..c3949fb316 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -310,8 +310,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, static void riscv_sifive_u_init(MachineState *machine) { const struct MemmapEntry *memmap = sifive_u_memmap; - - SiFiveUState *s = g_new0(SiFiveUState, 1); + SiFiveUState *s = RISCV_U_MACHINE(machine); MemoryRegion *system_memory = get_system_memory(); MemoryRegion *main_mem = g_new(MemoryRegion, 1); MemoryRegion *flash0 = g_new(MemoryRegion, 1); @@ -545,8 +544,15 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size); } -static void riscv_sifive_u_machine_init(MachineClass *mc) +static void riscv_sifive_u_machine_instance_init(Object *obj) +{ + +} + +static void riscv_sifive_u_machine_class_init(ObjectClass *oc, void *data) { + MachineClass *mc = MACHINE_CLASS(oc); + mc->desc = "RISC-V Board compatible with SiFive U SDK"; mc->init = riscv_sifive_u_init; mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT; @@ -554,7 +560,20 @@ static void riscv_sifive_u_machine_init(MachineClass *mc) mc->default_cpus = mc->min_cpus; } -DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init) +static const TypeInfo riscv_sifive_u_machine_init_typeinfo = { + .name = MACHINE_TYPE_NAME("sifive_u"), + .parent = TYPE_MACHINE, + .class_init = riscv_sifive_u_machine_class_init, + .instance_init = riscv_sifive_u_machine_instance_init, + .instance_size = sizeof(SiFiveUState), +}; + +static void riscv_sifive_u_machine_init_register_types(void) +{ + type_register_static(&riscv_sifive_u_machine_init_typeinfo); +} + +type_init(riscv_sifive_u_machine_init_register_types) static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data) { diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 2a08e2a5db..a921079fbe 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -44,12 +44,17 @@ typedef struct SiFiveUSoCState { CadenceGEMState gem; } SiFiveUSoCState; +#define TYPE_RISCV_U_MACHINE MACHINE_TYPE_NAME("sifive_u") +#define RISCV_U_MACHINE(obj) \ + OBJECT_CHECK(SiFiveUState, (obj), TYPE_RISCV_U_MACHINE) + typedef struct SiFiveUState { /*< private >*/ - SysBusDevice parent_obj; + MachineState parent_obj; /*< public >*/ SiFiveUSoCState soc; + void *fdt; int fdt_size; } SiFiveUState; -- 2.23.0