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Wed, 7 Apr 2021 19:33:05 +0000 (GMT) Received: from [9.80.221.20] (unknown [9.80.221.20]) by b03ledav004.gho.boulder.ibm.com (Postfix) with ESMTP; Wed, 7 Apr 2021 19:33:05 +0000 (GMT) Subject: Re: [PATCH 08/24] tests/qtest: Add test for Aspeed HACE To: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= , Peter Maydell References: <20210407171637.777743-1-clg@kaod.org> <20210407171637.777743-9-clg@kaod.org> From: Klaus Heinrich Kiwi Message-ID: <96574978-a20e-2bb0-7b4d-77ae3327ce4c@linux.vnet.ibm.com> Date: Wed, 7 Apr 2021 16:33:04 -0300 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.9.0 MIME-Version: 1.0 In-Reply-To: <20210407171637.777743-9-clg@kaod.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: LcyfG98n9BpU2v90z_pTOny4Pcb5cVb2 X-Proofpoint-ORIG-GUID: qMglkTyVQLTD8MRgKgdxOBIxg0fiBmxA X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-04-07_10:2021-04-07, 2021-04-07 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 mlxlogscore=999 malwarescore=0 lowpriorityscore=0 suspectscore=0 phishscore=0 adultscore=0 priorityscore=1501 spamscore=0 impostorscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104060000 definitions=main-2104070135 Received-SPF: none client-ip=148.163.156.1; envelope-from=klaus@linux.vnet.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jeffery , Thomas Huth , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Joel Stanley Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 4/7/2021 2:16 PM, Cédric Le Goater wrote: > From: Joel Stanley > > This adds a test for the Aspeed Hash and Crypto (HACE) engine. It tests > the currently implemented behavior of the hash functionality. > > The tests are similar, but are cut/pasted instead of broken out into a > common function so the assert machinery produces useful output when a > test fails. > > Signed-off-by: Joel Stanley > Reviewed-by: Cédric Le Goater > Acked-by: Thomas Huth > [ clg: - qtest_quit() fix ] > Signed-off-by: Cédric Le Goater > Message-Id: <20210324070955.125941-4-joel@jms.id.au> > Signed-off-by: Cédric Le Goater Reviewed-by: Klaus Heinrich Kiwi > --- > tests/qtest/aspeed_hace-test.c | 321 +++++++++++++++++++++++++++++++++ > MAINTAINERS | 1 + > tests/qtest/meson.build | 3 + > 3 files changed, 325 insertions(+) > create mode 100644 tests/qtest/aspeed_hace-test.c > > diff --git a/tests/qtest/aspeed_hace-test.c b/tests/qtest/aspeed_hace-test.c > new file mode 100644 > index 000000000000..675774e96eb9 > --- /dev/null > +++ b/tests/qtest/aspeed_hace-test.c > @@ -0,0 +1,321 @@ > +/* > + * QTest testcase for the ASPEED Hash and Crypto Engine > + * > + * SPDX-License-Identifier: GPL-2.0-or-later > + * Copyright 2021 IBM Corp. > + */ > + > +#include "qemu/osdep.h" > + > +#include "libqos/libqtest.h" > +#include "qemu-common.h" > +#include "qemu/bitops.h" > + > +#define HACE_CMD 0x10 > +#define HACE_SHA_BE_EN BIT(3) > +#define HACE_MD5_LE_EN BIT(2) > +#define HACE_ALGO_MD5 0 > +#define HACE_ALGO_SHA1 BIT(5) > +#define HACE_ALGO_SHA224 BIT(6) > +#define HACE_ALGO_SHA256 (BIT(4) | BIT(6)) > +#define HACE_ALGO_SHA512 (BIT(5) | BIT(6)) > +#define HACE_ALGO_SHA384 (BIT(5) | BIT(6) | BIT(10)) > +#define HACE_SG_EN BIT(18) > + > +#define HACE_STS 0x1c > +#define HACE_RSA_ISR BIT(13) > +#define HACE_CRYPTO_ISR BIT(12) > +#define HACE_HASH_ISR BIT(9) > +#define HACE_RSA_BUSY BIT(2) > +#define HACE_CRYPTO_BUSY BIT(1) > +#define HACE_HASH_BUSY BIT(0) > +#define HACE_HASH_SRC 0x20 > +#define HACE_HASH_DIGEST 0x24 > +#define HACE_HASH_KEY_BUFF 0x28 > +#define HACE_HASH_DATA_LEN 0x2c > +#define HACE_HASH_CMD 0x30 > + > +/* > + * Test vector is the ascii "abc" > + * > + * Expected results were generated using command line utitiles: > + * > + * echo -n -e 'abc' | dd of=/tmp/test > + * for hash in sha512sum sha256sum md5sum; do $hash /tmp/test; done > + * > + */ > +static const uint8_t test_vector[] = {0x61, 0x62, 0x63}; > + > +static const uint8_t test_result_sha512[] = { > + 0xdd, 0xaf, 0x35, 0xa1, 0x93, 0x61, 0x7a, 0xba, 0xcc, 0x41, 0x73, 0x49, > + 0xae, 0x20, 0x41, 0x31, 0x12, 0xe6, 0xfa, 0x4e, 0x89, 0xa9, 0x7e, 0xa2, > + 0x0a, 0x9e, 0xee, 0xe6, 0x4b, 0x55, 0xd3, 0x9a, 0x21, 0x92, 0x99, 0x2a, > + 0x27, 0x4f, 0xc1, 0xa8, 0x36, 0xba, 0x3c, 0x23, 0xa3, 0xfe, 0xeb, 0xbd, > + 0x45, 0x4d, 0x44, 0x23, 0x64, 0x3c, 0xe8, 0x0e, 0x2a, 0x9a, 0xc9, 0x4f, > + 0xa5, 0x4c, 0xa4, 0x9f}; > + > +static const uint8_t test_result_sha256[] = { > + 0xba, 0x78, 0x16, 0xbf, 0x8f, 0x01, 0xcf, 0xea, 0x41, 0x41, 0x40, 0xde, > + 0x5d, 0xae, 0x22, 0x23, 0xb0, 0x03, 0x61, 0xa3, 0x96, 0x17, 0x7a, 0x9c, > + 0xb4, 0x10, 0xff, 0x61, 0xf2, 0x00, 0x15, 0xad}; > + > +static const uint8_t test_result_md5[] = { > + 0x90, 0x01, 0x50, 0x98, 0x3c, 0xd2, 0x4f, 0xb0, 0xd6, 0x96, 0x3f, 0x7d, > + 0x28, 0xe1, 0x7f, 0x72}; > + > + > +static void write_regs(QTestState *s, uint32_t base, uint32_t src, > + uint32_t length, uint32_t out, uint32_t method) > +{ > + qtest_writel(s, base + HACE_HASH_SRC, src); > + qtest_writel(s, base + HACE_HASH_DIGEST, out); > + qtest_writel(s, base + HACE_HASH_DATA_LEN, length); > + qtest_writel(s, base + HACE_HASH_CMD, HACE_SHA_BE_EN | method); > +} > + > +static void test_md5(const char *machine, const uint32_t base, > + const uint32_t src_addr) > + > +{ > + QTestState *s = qtest_init(machine); > + > + uint32_t digest_addr = src_addr + 0x01000000; > + uint8_t digest[16] = {0}; > + > + /* Check engine is idle, no busy or irq bits set */ > + g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); > + > + /* Write test vector into memory */ > + qtest_memwrite(s, src_addr, test_vector, sizeof(test_vector)); > + > + write_regs(s, base, src_addr, sizeof(test_vector), digest_addr, HACE_ALGO_MD5); > + > + /* Check hash IRQ status is asserted */ > + g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200); > + > + /* Clear IRQ status and check status is deasserted */ > + qtest_writel(s, base + HACE_STS, 0x00000200); > + g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); > + > + /* Read computed digest from memory */ > + qtest_memread(s, digest_addr, digest, sizeof(digest)); > + > + /* Check result of computation */ > + g_assert_cmpmem(digest, sizeof(digest), > + test_result_md5, sizeof(digest)); > + > + qtest_quit(s); > +} > + > +static void test_sha256(const char *machine, const uint32_t base, > + const uint32_t src_addr) > +{ > + QTestState *s = qtest_init(machine); > + > + const uint32_t digest_addr = src_addr + 0x1000000; > + uint8_t digest[32] = {0}; > + > + /* Check engine is idle, no busy or irq bits set */ > + g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); > + > + /* Write test vector into memory */ > + qtest_memwrite(s, src_addr, test_vector, sizeof(test_vector)); > + > + write_regs(s, base, src_addr, sizeof(test_vector), digest_addr, HACE_ALGO_SHA256); > + > + /* Check hash IRQ status is asserted */ > + g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200); > + > + /* Clear IRQ status and check status is deasserted */ > + qtest_writel(s, base + HACE_STS, 0x00000200); > + g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); > + > + /* Read computed digest from memory */ > + qtest_memread(s, digest_addr, digest, sizeof(digest)); > + > + /* Check result of computation */ > + g_assert_cmpmem(digest, sizeof(digest), > + test_result_sha256, sizeof(digest)); > + > + qtest_quit(s); > +} > + > +static void test_sha512(const char *machine, const uint32_t base, > + const uint32_t src_addr) > +{ > + QTestState *s = qtest_init(machine); > + > + const uint32_t digest_addr = src_addr + 0x1000000; > + uint8_t digest[64] = {0}; > + > + /* Check engine is idle, no busy or irq bits set */ > + g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); > + > + /* Write test vector into memory */ > + qtest_memwrite(s, src_addr, test_vector, sizeof(test_vector)); > + > + write_regs(s, base, src_addr, sizeof(test_vector), digest_addr, HACE_ALGO_SHA512); > + > + /* Check hash IRQ status is asserted */ > + g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200); > + > + /* Clear IRQ status and check status is deasserted */ > + qtest_writel(s, base + HACE_STS, 0x00000200); > + g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); > + > + /* Read computed digest from memory */ > + qtest_memread(s, digest_addr, digest, sizeof(digest)); > + > + /* Check result of computation */ > + g_assert_cmpmem(digest, sizeof(digest), > + test_result_sha512, sizeof(digest)); > + > + qtest_quit(s); > +} > + > +struct masks { > + uint32_t src; > + uint32_t dest; > + uint32_t len; > +}; > + > +static const struct masks ast2600_masks = { > + .src = 0x7fffffff, > + .dest = 0x7ffffff8, > + .len = 0x0fffffff, > +}; > + > +static const struct masks ast2500_masks = { > + .src = 0x3fffffff, > + .dest = 0x3ffffff8, > + .len = 0x0fffffff, > +}; > + > +static const struct masks ast2400_masks = { > + .src = 0x0fffffff, > + .dest = 0x0ffffff8, > + .len = 0x0fffffff, > +}; > + > +static void test_addresses(const char *machine, const uint32_t base, > + const struct masks *expected) > +{ > + QTestState *s = qtest_init(machine); > + > + /* > + * Check command mode is zero, meaning engine is in direct access mode, > + * as this affects the masking behavior of the HASH_SRC register. > + */ > + g_assert_cmphex(qtest_readl(s, base + HACE_CMD), ==, 0); > + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC), ==, 0); > + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), ==, 0); > + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), ==, 0); > + > + > + /* Check that the address masking is correct */ > + qtest_writel(s, base + HACE_HASH_SRC, 0xffffffff); > + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC), ==, expected->src); > + > + qtest_writel(s, base + HACE_HASH_DIGEST, 0xffffffff); > + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), ==, expected->dest); > + > + qtest_writel(s, base + HACE_HASH_DATA_LEN, 0xffffffff); > + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), ==, expected->len); > + > + /* Reset to zero */ > + qtest_writel(s, base + HACE_HASH_SRC, 0); > + qtest_writel(s, base + HACE_HASH_DIGEST, 0); > + qtest_writel(s, base + HACE_HASH_DATA_LEN, 0); > + > + /* Check that all bits are now zero */ > + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC), ==, 0); > + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), ==, 0); > + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), ==, 0); > + > + qtest_quit(s); > +} > + > +/* ast2600 */ > +static void test_md5_ast2600(void) > +{ > + test_md5("-machine ast2600-evb", 0x1e6d0000, 0x80000000); > +} > + > +static void test_sha256_ast2600(void) > +{ > + test_sha256("-machine ast2600-evb", 0x1e6d0000, 0x80000000); > +} > + > +static void test_sha512_ast2600(void) > +{ > + test_sha512("-machine ast2600-evb", 0x1e6d0000, 0x80000000); > +} > + > +static void test_addresses_ast2600(void) > +{ > + test_addresses("-machine ast2600-evb", 0x1e6d0000, &ast2600_masks); > +} > + > +/* ast2500 */ > +static void test_md5_ast2500(void) > +{ > + test_md5("-machine ast2500-evb", 0x1e6e3000, 0x80000000); > +} > + > +static void test_sha256_ast2500(void) > +{ > + test_sha256("-machine ast2500-evb", 0x1e6e3000, 0x80000000); > +} > + > +static void test_sha512_ast2500(void) > +{ > + test_sha512("-machine ast2500-evb", 0x1e6e3000, 0x80000000); > +} > + > +static void test_addresses_ast2500(void) > +{ > + test_addresses("-machine ast2500-evb", 0x1e6e3000, &ast2500_masks); > +} > + > +/* ast2400 */ > +static void test_md5_ast2400(void) > +{ > + test_md5("-machine palmetto-bmc", 0x1e6e3000, 0x40000000); > +} > + > +static void test_sha256_ast2400(void) > +{ > + test_sha256("-machine palmetto-bmc", 0x1e6e3000, 0x40000000); > +} > + > +static void test_sha512_ast2400(void) > +{ > + test_sha512("-machine palmetto-bmc", 0x1e6e3000, 0x40000000); > +} > + > +static void test_addresses_ast2400(void) > +{ > + test_addresses("-machine palmetto-bmc", 0x1e6e3000, &ast2400_masks); > +} > + > +int main(int argc, char **argv) > +{ > + g_test_init(&argc, &argv, NULL); > + > + qtest_add_func("ast2600/hace/addresses", test_addresses_ast2600); > + qtest_add_func("ast2600/hace/sha512", test_sha512_ast2600); > + qtest_add_func("ast2600/hace/sha256", test_sha256_ast2600); > + qtest_add_func("ast2600/hace/md5", test_md5_ast2600); > + > + qtest_add_func("ast2500/hace/addresses", test_addresses_ast2500); > + qtest_add_func("ast2500/hace/sha512", test_sha512_ast2500); > + qtest_add_func("ast2500/hace/sha256", test_sha256_ast2500); > + qtest_add_func("ast2500/hace/md5", test_md5_ast2500); > + > + qtest_add_func("ast2400/hace/addresses", test_addresses_ast2400); > + qtest_add_func("ast2400/hace/sha512", test_sha512_ast2400); > + qtest_add_func("ast2400/hace/sha256", test_sha256_ast2400); > + qtest_add_func("ast2400/hace/md5", test_md5_ast2400); > + > + return g_test_run(); > +} > diff --git a/MAINTAINERS b/MAINTAINERS > index 58f342108e9e..63c050ddc84a 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -1026,6 +1026,7 @@ F: include/hw/misc/pca9552*.h > F: hw/net/ftgmac100.c > F: include/hw/net/ftgmac100.h > F: docs/system/arm/aspeed.rst > +F: tests/qtest/*aspeed* > > NRF51 > M: Joel Stanley > diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build > index 902cfef7cb2f..84b3219c15c6 100644 > --- a/tests/qtest/meson.build > +++ b/tests/qtest/meson.build > @@ -163,12 +163,15 @@ qtests_npcm7xx = \ > 'npcm7xx_timer-test', > 'npcm7xx_watchdog_timer-test'] + \ > (slirp.found() ? ['npcm7xx_emc-test'] : []) > +qtests_aspeed = \ > + ['aspeed_hace-test'] > qtests_arm = \ > (config_all_devices.has_key('CONFIG_MPS2') ? ['sse-timer-test'] : []) + \ > (config_all_devices.has_key('CONFIG_CMSDK_APB_DUALTIMER') ? ['cmsdk-apb-dualtimer-test'] : []) + \ > (config_all_devices.has_key('CONFIG_CMSDK_APB_TIMER') ? ['cmsdk-apb-timer-test'] : []) + \ > (config_all_devices.has_key('CONFIG_CMSDK_APB_WATCHDOG') ? ['cmsdk-apb-watchdog-test'] : []) + \ > (config_all_devices.has_key('CONFIG_PFLASH_CFI02') ? ['pflash-cfi02-test'] : []) + \ > + (config_all_devices.has_key('CONFIG_ASPEED_SOC') ? qtests_aspeed : []) + \ > (config_all_devices.has_key('CONFIG_NPCM7XX') ? qtests_npcm7xx : []) + \ > ['arm-cpu-features', > 'microbit-test', > -- Klaus Heinrich Kiwi