From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: Luc Michel <luc@lmichel.fr>, qemu-devel@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>,
Andrei Warkentin <andrey.warkentin@gmail.com>,
Andrew Baumann <Andrew.Baumann@microsoft.com>,
qemu-arm@nongnu.org, Pete Batard <pete@akeo.ie>,
Samer El-Haj-Mahmoud <samer@elhajmahmoud.com>,
Ard Biesheuvel <ardb@kernel.org>
Subject: Re: [PATCH 08/14] hw/misc/bcm2835_cprman: implement PLL channels behaviour
Date: Sat, 26 Sep 2020 23:36:51 +0200 [thread overview]
Message-ID: <973df115-4f26-66ba-051a-142d2901293d@amsat.org> (raw)
In-Reply-To: <20200925101731.2159827-9-luc@lmichel.fr>
On 9/25/20 12:17 PM, Luc Michel wrote:
> A PLL channel is able to further divide the generated PLL frequency. The
You can move the 'The' to the next line =)
> divider is given in the ctrl_a2w register. Some channels have a
s/a/an/
> additional fixed divider which is always applied to the signal.
>
> Signed-off-by: Luc Michel <luc@lmichel.fr>
> ---
> hw/misc/bcm2835_cprman.c | 33 ++++++++++++++++++++++++++++++++-
> 1 file changed, 32 insertions(+), 1 deletion(-)
>
> diff --git a/hw/misc/bcm2835_cprman.c b/hw/misc/bcm2835_cprman.c
> index 2c70a3f317..e644aeb2b5 100644
> --- a/hw/misc/bcm2835_cprman.c
> +++ b/hw/misc/bcm2835_cprman.c
> @@ -132,13 +132,44 @@ static const TypeInfo cprman_pll_info = {
> };
>
>
> /* PLL channel */
>
> +static bool pll_channel_is_enabled(CprmanPLLChannelState *channel)
> +{
> + /*
> + * XXX I'm not sure of the purpose of the LOAD field. The Linux driver does
> + * not set it when enabling the channel, but does clear it when disabling
> + * it.
Cc'ed firmware developers who might have a clue.
> + */
> + return !FIELD_EX32(*channel->reg_a2w_ctrl, A2W_PLLx_CHANNELy, DISABLE)
> + && !(*channel->reg_cm & channel->hold_mask);
> +}
> +
> static void pll_channel_update(CprmanPLLChannelState *channel)
> {
> - clock_update(channel->out, 0);
> + uint64_t freq, div;
> +
> + if (!pll_channel_is_enabled(channel)) {
> + clock_update(channel->out, 0);
> + return;
> + }
> +
> + div = FIELD_EX32(*channel->reg_a2w_ctrl, A2W_PLLx_CHANNELy, DIV);
> +
> + if (!div) {
> + /*
> + * It seems that when the divider value is 0, it is considered as
> + * being maximum by the hardware (see the Linux driver).
> + */
> + div = R_A2W_PLLx_CHANNELy_DIV_MASK;
> + }
> +
> + /* Some channels have an additional fixed divider */
> + freq = clock_get_hz(channel->pll_in) / (div * channel->fixed_divider);
> +
> + clock_update_hz(channel->out, freq);
> }
>
> /* Update a PLL and all its channels */
> static void pll_update_all_channels(BCM2835CprmanState *s,
> CprmanPLLState *pll)
>
next prev parent reply other threads:[~2020-09-26 21:37 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-25 10:17 [PATCH 00/14] raspi: add the bcm2835 cprman clock manager Luc Michel
2020-09-25 10:17 ` [PATCH 01/14] hw/core/clock: provide the VMSTATE_ARRAY_CLOCK macro Luc Michel
2020-09-26 20:36 ` Philippe Mathieu-Daudé
2020-09-28 8:38 ` Damien Hedde
2020-09-25 10:17 ` [PATCH 02/14] hw/core/clock: trace clock values in Hz instead of ns Luc Michel
2020-09-26 20:36 ` Philippe Mathieu-Daudé
2020-09-28 8:42 ` Damien Hedde
2020-09-25 10:17 ` [PATCH 03/14] hw/arm/raspi: fix cprman base address Luc Michel
2020-09-26 21:04 ` Philippe Mathieu-Daudé
2020-09-25 10:17 ` [PATCH 04/14] hw/arm/raspi: add a skeleton implementation of the cprman Luc Michel
2020-09-26 21:05 ` Philippe Mathieu-Daudé
2020-09-28 8:45 ` Luc Michel
2020-10-02 14:37 ` Philippe Mathieu-Daudé
2020-10-03 11:54 ` Luc Michel
2020-10-03 18:14 ` Philippe Mathieu-Daudé
2020-09-25 10:17 ` [PATCH 05/14] hw/misc/bcm2835_cprman: add a PLL skeleton implementation Luc Michel
2020-09-26 21:17 ` Philippe Mathieu-Daudé
2020-09-25 10:17 ` [PATCH 06/14] hw/misc/bcm2835_cprman: implement PLLs behaviour Luc Michel
2020-09-26 21:26 ` Philippe Mathieu-Daudé
2020-09-25 10:17 ` [PATCH 07/14] hw/misc/bcm2835_cprman: add a PLL channel skeleton implementation Luc Michel
2020-09-26 21:32 ` Philippe Mathieu-Daudé
2020-09-25 10:17 ` [PATCH 08/14] hw/misc/bcm2835_cprman: implement PLL channels behaviour Luc Michel
2020-09-26 21:36 ` Philippe Mathieu-Daudé [this message]
2020-09-25 10:17 ` [PATCH 09/14] hw/misc/bcm2835_cprman: add a clock mux skeleton implementation Luc Michel
2020-10-02 14:42 ` Philippe Mathieu-Daudé
2020-10-02 15:34 ` Philippe Mathieu-Daudé
2020-10-04 19:34 ` Luc Michel
2020-10-04 20:17 ` Philippe Mathieu-Daudé
2020-09-25 10:17 ` [PATCH 10/14] hw/misc/bcm2835_cprman: implement clock mux behaviour Luc Michel
2020-09-26 21:40 ` Philippe Mathieu-Daudé
2020-10-02 14:51 ` Philippe Mathieu-Daudé
2020-10-04 18:37 ` Luc Michel
2020-10-05 19:50 ` Luc Michel
2020-09-25 10:17 ` [PATCH 11/14] hw/misc/bcm2835_cprman: add the DSI0HSCK multiplexer Luc Michel
2020-10-02 14:55 ` Philippe Mathieu-Daudé
2020-09-25 10:17 ` [PATCH 12/14] hw/misc/bcm2835_cprman: add sane reset values to the registers Luc Michel
2020-09-25 10:17 ` [RFC PATCH 13/14] hw/char/pl011: add a clock input Luc Michel
2020-09-25 10:36 ` Philippe Mathieu-Daudé
2020-09-25 10:17 ` [RFC PATCH 14/14] hw/arm/bcm2835_peripherals: connect the UART clock Luc Michel
2020-09-25 11:56 ` [PATCH 00/14] raspi: add the bcm2835 cprman clock manager no-reply
2020-09-25 12:55 ` Philippe Mathieu-Daudé
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