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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id q19sm9297652pfk.49.2021.08.02.15.23.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 02 Aug 2021 15:23:09 -0700 (PDT) Subject: Re: [PATCH 0/2] arm: Implement M-profile trapping on division by zero To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20210730151636.17254-1-peter.maydell@linaro.org> From: Richard Henderson Message-ID: <98703606-f970-774f-f8ac-5bad2e67013d@linaro.org> Date: Mon, 2 Aug 2021 12:23:05 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <20210730151636.17254-1-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 7/30/21 5:16 AM, Peter Maydell wrote: > Unlike A-profile, for M-profile the UDIV and SDIV insns can be > configured to raise an exception on division by zero, using the CCR > DIV_0_TRP bit. This patchset implements that missing functionality > by having the udiv and sdiv helpers raise an exception if needed. > > Some questions: > > Is it worth allowing A-profile to retain the mildly better codegen it > gets from not having to pass in 'env' and marking the helper as > no-side-effects (ie having M-specific udiv/sdiv helpers) ? Probably not. > Is it worth inlining either udiv or sdiv for the A-profile case? Probably not. > mov_i32 tmp3,r2 > mov_i32 tmp6,r3 > movcond_i32 tmp3,tmp6,$0x0,$0x0,tmp3,eq > movcond_i32 tmp6,tmp6,$0x0,$0x1,tmp6,eq > mov_i32 tmp7,$0x0 > divu2_i32 tmp3,tmp7,tmp3,tmp7,tmp6 > mov_i32 r3,tmp3 > > but the x86 code is > 0x7f5f1807dc0c: 45 33 f6 xorl %r14d, %r14d > 0x7f5f1807dc0f: 45 85 ed testl %r13d, %r13d > 0x7f5f1807dc12: 45 0f 44 e6 cmovel %r14d, %r12d At the start of the first movcond, $0x0 is not allocated to a register, and the constraints allow a constant for argument 3. Then, constraints do not allow a constant for argument 4 so we load $0x0 into a register. > 0x7f5f1807dc16: 41 bf 01 00 00 00 movl $1, %r15d > 0x7f5f1807dc1c: 45 3b ee cmpl %r14d, %r13d > 0x7f5f1807dc1f: 45 0f 44 ef cmovel %r15d, %r13d At the start of the second movcond, $0x0 is loaded into a register, so we use it. > (Ideally of > course it would notice that it already had generated the condition > check and not repeat it.) Yep. r~