From: Xiaoyao Li <xiaoyao.li@intel.com>
To: Eduardo Habkost <ehabkost@redhat.com>
Cc: qemu-devel@nongnu.org, Paolo Bonzini <pbonzini@redhat.com>,
Cathy Zhang <cathy.zhang@intel.com>,
Richard Henderson <rth@twiddle.net>
Subject: Re: [PATCH 2/2] target/i386: Add missed features to Cooperlake CPU model
Date: Tue, 25 Aug 2020 08:20:35 +0800 [thread overview]
Message-ID: <9cdaaa8d-4ce2-88c7-2400-eed62ffe779b@intel.com> (raw)
In-Reply-To: <20200824220759.GS642093@habkost.net>
On 8/25/2020 6:07 AM, Eduardo Habkost wrote:
> On Wed, Dec 25, 2019 at 02:30:18PM +0800, Xiaoyao Li wrote:
>> It lacks VMX features and two security feature bits (disclosed recently) in
>> MSR_IA32_ARCH_CAPABILITIES in current Cooperlake CPU model, so add them.
>>
>> Fixes: 22a866b6166d ("i386: Add new CPU model Cooperlake")
>> Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
>> ---
>> target/i386/cpu.c | 51 ++++++++++++++++++++++++++++++++++++++++++++++-
>> 1 file changed, 50 insertions(+), 1 deletion(-)
>>
>> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
>> index e1eb9f473989..c9798ac8652b 100644
>> --- a/target/i386/cpu.c
>> +++ b/target/i386/cpu.c
>> @@ -3198,7 +3198,8 @@ static X86CPUDefinition builtin_x86_defs[] = {
>> CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES,
>> .features[FEAT_ARCH_CAPABILITIES] =
>> MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL |
>> - MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO,
>> + MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO |
>> + MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO,
>
> This seems to break on some Cooperlake hosts, see:
>
> https://bugzilla.redhat.com/show_bug.cgi?id=1860743
>
> Are all Cooperlake hosts supposed to have TAA_NO set? Are there
> hosts where this requires a microcode update to be installed?
>
All the production CPX in market should have IAA_NO bit. We can check it
directly with rdmsr(0x10a).
The problem of this issue is due to commit db616173d787 ("x86/tsx: Add
config options to set tsx=on|off|auto"), which sets the default to "off"
for 100% safety. However, default to off may cause noticeable
regressions on TSX safe platform, e.g., CPX.
Maybe we need to set CONFIG_X86_INTEL_TSX_MODE_AUTO=y for OSV released
kernel?
next prev parent reply other threads:[~2020-08-25 0:25 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-25 6:30 [PATCH 0/2] Fix Cooperlake CPU model Xiaoyao Li
2019-12-25 6:30 ` [PATCH 1/2] target/i386: Add new bit definitions of MSR_IA32_ARCH_CAPABILITIES Xiaoyao Li
2019-12-25 6:30 ` [PATCH 2/2] target/i386: Add missed features to Cooperlake CPU model Xiaoyao Li
2020-08-24 22:07 ` Eduardo Habkost
2020-08-25 0:20 ` Xiaoyao Li [this message]
2020-08-25 14:01 ` Eduardo Habkost
2020-08-26 2:43 ` Xiaoyao Li
2020-01-07 13:31 ` [PATCH 0/2] Fix " Paolo Bonzini
2020-03-16 1:39 ` Zhang, Cathy
2020-03-16 8:41 ` Paolo Bonzini
2020-03-16 10:19 ` Zhang, Cathy
2020-03-16 10:24 ` Paolo Bonzini
2020-03-16 11:43 ` Zhang, Cathy
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