messages from 2021-10-21 21:25:19 to 2021-10-22 17:48:24 UTC [more...]
[PATCH v3 00/48] tcg: optimize redundant sign extensions
2021-10-22 17:35 UTC (61+ messages)
` [PATCH v3 02/48] tcg/optimize: Split out OptContext
` [PATCH v3 03/48] tcg/optimize: Remove do_default label
` [PATCH v3 05/48] tcg/optimize: Move prev_mb into OptContext
` [PATCH v3 10/48] tcg/optimize: Change fail return for do_constant_folding_cond*
` [PATCH v3 11/48] tcg/optimize: Return true from tcg_opt_gen_{mov, movi}
` [PATCH v3 14/48] tcg/optimize: Split out fold_mb, fold_qemu_{ld,st}
` [PATCH v3 17/48] tcg/optimize: Split out fold_brcond2
` [PATCH v3 18/48] tcg/optimize: Split out fold_brcond
` [PATCH v3 19/48] tcg/optimize: Split out fold_setcond
` [PATCH v3 20/48] tcg/optimize: Split out fold_mulu2_i32
` [PATCH v3 21/48] tcg/optimize: Split out fold_addsub2_i32
` [PATCH v3 22/48] tcg/optimize: Split out fold_movcond
` [PATCH v3 23/48] tcg/optimize: Split out fold_extract2
` [PATCH v3 24/48] tcg/optimize: Split out fold_extract, fold_sextract
` [PATCH v3 25/48] tcg/optimize: Split out fold_deposit
` [PATCH v3 26/48] tcg/optimize: Split out fold_count_zeros
` [PATCH v3 27/48] tcg/optimize: Split out fold_bswap
` [PATCH v3 28/48] tcg/optimize: Split out fold_dup, fold_dup2
` [PATCH v3 29/48] tcg/optimize: Split out fold_mov
` [PATCH v3 30/48] tcg/optimize: Split out fold_xx_to_i
` [PATCH v3 31/48] tcg/optimize: Split out fold_xx_to_x
` [PATCH v3 32/48] tcg/optimize: Split out fold_xi_to_i
` [PATCH v3 33/48] tcg/optimize: Add type to OptContext
` [PATCH v3 34/48] tcg/optimize: Split out fold_to_not
` [PATCH v3 35/48] tcg/optimize: Split out fold_sub_to_neg
` [PATCH v3 36/48] tcg/optimize: Split out fold_xi_to_x
` [PATCH v3 37/48] tcg/optimize: Split out fold_ix_to_i
` [PATCH v3 38/48] tcg/optimize: Split out fold_masks
` [PATCH v3 39/48] tcg/optimize: Expand fold_mulu2_i32 to all 4-arg multiplies
` [PATCH v3 40/48] tcg/optimize: Expand fold_addsub2_i32 to 64-bit ops
` [PATCH v3 41/48] tcg/optimize: Sink commutative operand swapping into fold functions
` [PATCH v3 42/48] tcg/optimize: Add more simplifications for orc
` [PATCH v3 43/48] tcg/optimize: Stop forcing z_mask to "garbage" for 32-bit values
` [PATCH v3 44/48] tcg/optimize: Optimize sign extensions
` [PATCH v3 45/48] tcg/optimize: Propagate sign info for logical operations
` [PATCH v3 46/48] tcg/optimize: Propagate sign info for setcond
` [PATCH v3 47/48] tcg/optimize: Propagate sign info for bit counting
` [PATCH v3 48/48] tcg/optimize: Propagate sign info for shifting
[RFC PATCH v1 1/2] riscv: Add preliminary infra for custom instrcution handling
2021-10-22 17:24 UTC (8+ messages)
` [RFC PATCH v1 2/2] Enable custom instruction suport for Andes A25 and AX25 CPU model
[PATCH v4] isa-applesmc: provide OSK forwarding on Apple hosts
2021-10-22 16:14 UTC
[PATCH v3] isa-applesmc: provide OSK forwarding on Apple hosts
2021-10-22 16:10 UTC (4+ messages)
[PATCH v3 0/3] plugins: add a drcov plugin
2021-10-22 16:07 UTC (4+ messages)
` [PATCH v3 1/3] src/plugins: sorted list
` [PATCH v3 2/3] This patch adds helper functions to the drcov plugin
` [PATCH v3 3/3] contrib/plugins: add a "
[PULL 0/9] Q800 patches
2021-10-22 16:01 UTC (11+ messages)
` [PULL 1/9] mac_via: update comment for VIA1B_vMystery bit
` [PULL 2/9] q800: move VIA1 IRQ from level 1 to level 6
` [PULL 3/9] q800: use GLUE IRQ numbers instead of IRQ level for GLUE IRQs
` [PULL 4/9] mac_via: add GPIO for A/UX mode
` [PULL 5/9] q800: wire up auxmode GPIO to GLUE
` [PULL 6/9] q800: route SONIC on-board Ethernet IRQ via nubus IRQ 9 in classic mode
` [PULL 7/9] q800: wire up remaining IRQs "
` [PULL 8/9] q800: add NMI handler
` [PULL 9/9] q800: drop 8-bit graphic_depth check for Apple 21 inch display
[RFC PATCH v5 0/3] riscv: Add preliminary custom CSR support
2021-10-22 15:59 UTC (14+ messages)
` [RFC PATCH v5 1/3] riscv: Adding Andes A25 and AX25 cpu models
` [RFC PATCH v5 2/3] riscv: Introduce custom CSR hooks to riscv_csrrw()
` [RFC PATCH v5 3/3] riscv: Enable custom CSR support for Andes AX25 and A25 CPUs
[PATCH v6 00/15] target/riscv: Rationalize XLEN and operand length
2021-10-22 15:50 UTC (3+ messages)
[PATCH v4] tests: qtest: Add virtio-iommu test
2021-10-22 15:41 UTC (2+ messages)
[RESEND PATCH 0/2] Fix machine parameter default_bus_bypass_iommu
2021-10-22 14:58 UTC (6+ messages)
` [RESEND PATCH 2/2] hw/i386: Rename default_bus_bypass_iommu
[PATCH v2 1/5] hw/riscv: virt: Don't use a macro for the PLIC configuration
2021-10-22 14:58 UTC (11+ messages)
` [PATCH v2 2/5] hw/riscv: boot: Add a PLIC config string function
` [PATCH v2 3/5] hw/riscv: sifive_u: Use the PLIC config helper function
` [PATCH v2 4/5] hw/riscv: microchip_pfsoc: "
` [PATCH v2 5/5] hw/riscv: virt: "
[PULL 00/33] riscv-to-apply queue
2021-10-22 13:38 UTC (34+ messages)
` [PULL 01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v
` [PULL 02/33] target/riscv: line up all of the registers in the info register dump
` [PULL 03/33] target/riscv: Fix orc.b implementation
` [PULL 04/33] hw/riscv: virt: Use machine->ram as the system memory
` [PULL 05/33] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh
` [PULL 06/33] target/riscv: Remove some unused macros
` [PULL 07/33] target/riscv: Organise the CPU properties
` [PULL 08/33] target/riscv: Move cpu_get_tb_cpu_state out of line
` [PULL 09/33] target/riscv: Create RISCVMXL enumeration
` [PULL 10/33] target/riscv: Split misa.mxl and misa.ext
` [PULL 11/33] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
` [PULL 12/33] target/riscv: Add MXL/SXL/UXL to TB_FLAGS
` [PULL 13/33] target/riscv: Use REQUIRE_64BIT in amo_check64
` [PULL 14/33] target/riscv: Properly check SEW in amo_op
` [PULL 15/33] target/riscv: Replace is_32bit with get_xl/get_xlen
` [PULL 16/33] target/riscv: Replace DisasContext.w with DisasContext.ol
` [PULL 17/33] target/riscv: Use gen_arith_per_ol for RVM
` [PULL 18/33] target/riscv: Adjust trans_rev8_32 for riscv64
` [PULL 19/33] target/riscv: Use gen_unary_per_ol for RVB
` [PULL 20/33] target/riscv: Use gen_shift*_per_ol for RVB, RVI
` [PULL 21/33] target/riscv: Use riscv_csrrw_debug for cpu_dump
` [PULL 22/33] target/riscv: Compute mstatus.sd on demand
` [PULL 23/33] hw/riscv: opentitan: Update to the latest build
` [PULL 24/33] hw/intc: Remove the Ibex PLIC
` [PULL 25/33] hw/intc: sifive_plic: Move the properties
` [PULL 26/33] hw/intc: sifive_plic: Cleanup the realize function
` [PULL 27/33] hw/intc: sifive_plic: Cleanup the irq_request function
` [PULL 28/33] hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id
` [PULL 29/33] hw/riscv: opentitan: "
` [PULL 30/33] hw/riscv: shakti_c: "
` [PULL 31/33] hw/riscv: sifive_e: "
` [PULL 32/33] hw/riscv: sifive_u: "
` [PULL 33/33] hw/riscv: spike: "
[PULL v2 00/44] pc,pci,virtio: features, fixes, tests
2021-10-22 13:04 UTC (3+ messages)
` [PULL v2 02/44] tests: qtest: add qtest_has_accel() to check if tested binary supports accelerator
[PULL 0/2] Seabios 20211022 patches
2021-10-22 12:14 UTC (3+ messages)
` [PULL 1/2] update seabios to master branch snapshot
` [PULL 2/2] update seabios binaries
configure --extra-cflags and --extra-ldflags values not propagating to meson?
2021-10-22 11:20 UTC
[PATCH 00/33] PowerISA v3.1 instruction batch
2021-10-22 11:13 UTC (3+ messages)
[PATCH v2] isa-applesmc: provide OSK forwarding on Apple hosts
2021-10-22 10:43 UTC (2+ messages)
[PATCH v2 0/5] SGX NUMA support plus vepc reset
2021-10-22 19:27 UTC (6+ messages)
` [PATCH v2 1/5] numa: Enable numa for SGX EPC sections
` [PATCH v2 2/5] monitor: Support 'info numa' command
` [PATCH v2 3/5] numa: Support SGX numa in the monitor and Libvirt interfaces
` [PATCH v2 4/5] doc: Add the SGX numa description
` [PATCH v2 5/5] sgx: Reset the vEPC regions during VM reboot
[PATCH v8 00/10] acpi: Error Record Serialization Table, ERST, support for QEMU
2021-10-22 10:25 UTC (5+ messages)
` [PATCH v8 04/10] ACPI ERST: header file for ERST
` [PATCH v8 07/10] ACPI ERST: create ACPI ERST table for pc/x86 machines
[RFC PATCH] plugins: try and make plugin_insn_append more ergonomic
2021-10-22 10:05 UTC
[PATCH v2 0/2] vfio: Some fixes about vfio-pci MMIO RAM mapping
2021-10-22 10:02 UTC (7+ messages)
` [PATCH v2 1/2] vfio/pci: Fix vfio-pci sub-page MMIO BAR mmaping in live migration
` [PATCH v2 2/2] vfio/common: Add trace point when a MMIO RAM section less than PAGE_SIZE
[PATCH] block/export/fuse.c: fix musl build
2021-10-22 9:52 UTC
plugins: Missing Store Exclusive Memory Accesses
2021-10-22 8:37 UTC (10+ messages)
[PATCH 0/8] pci/iommu: Fail early if vfio-pci detected before vIOMMU
2021-10-22 8:43 UTC (20+ messages)
` [PATCH 1/8] pci: Define pci_bus_dev_fn type
` [PATCH 3/8] pci: Use pci_for_each_device_under_bus*()
` [PATCH 4/8] pci: Define pci_bus_fn/pci_bus_ret_fn type
` [PATCH 7/8] pci: Add pci_for_each_device_all()
` [PATCH 8/8] x86-iommu: Fail early if vIOMMU specified after vfio-pci
[PULL 0/3] aspeed queue
2021-10-22 7:57 UTC (4+ messages)
` [PULL 1/3] aspeed: Add support for the fp5280g2-bmc board
` [PULL 2/3] aspeed/smc: Use a container for the flash mmio address space
` [PULL 3/3] speed/sdhci: Add trace events
[PATCH v2 0/5] aspeed/smc: Improve support for the alternate boot function
2021-10-22 7:05 UTC (5+ messages)
[PATCH v3 00/21] Adding partial support for 128-bit riscv target
2021-10-22 6:06 UTC (4+ messages)
` [PATCH v3 06/21] target/riscv: array for the 64 upper bits of 128-bit registers
[PATCH v5 1/8] target/riscv: zfh: half-precision load and store
2021-10-22 3:25 UTC (5+ messages)
[PATCH 00/31] Add Loongarch softmmu support
2021-10-22 2:25 UTC (3+ messages)
` [PATCH 01/31] target/loongarch: Upate the README for the softmmu
[PATCH v7 00/21] Add LoongArch linux-user emulation support
2021-10-22 2:04 UTC (11+ messages)
` [PATCH v7 02/21] target/loongarch: Add core definition
[PATCH v3 00/22] target/ppc: DFP instructions using decodetree
2021-10-21 23:23 UTC (27+ messages)
` [PATCH v3 03/22] host-utils: introduce uabs64()
` [PATCH v3 07/22] host-utils: add 128-bit quotient support to divu128/divs128
` [PATCH v3 08/22] host-utils: add unit tests for divu128/divs128
` [PATCH v3 12/22] target/ppc: Implement DCFFIXQQ
` [PATCH v3 15/22] target/ppc: Implement DCTFIXQQ
` [PATCH v3 16/22] target/ppc: Move dtstdc[q]/dtstdg[q] to decodetree
` [PATCH v3 17/22] target/ppc: Move d{add, sub, mul, div, iex}[q] "
` [PATCH v3 17/22] target/ppc: Move d{add,sub,mul,div,iex}[q] "
` [PATCH v3 18/22] target/ppc: Move dcmp{u, o}[q], dts{tex, tsf, tsfi}[q] "
` [PATCH v3 18/22] target/ppc: Move dcmp{u,o}[q],dts{tex,tsf,tsfi}[q] "
` [PATCH v3 19/22] target/ppc: Move dquai[q], drint{x, n}[q] "
` [PATCH v3 19/22] target/ppc: Move dquai[q], drint{x,n}[q] "
` [PATCH v3 20/22] target/ppc: Move dqua[q], drrnd[q] "
` [PATCH v3 21/22] target/ppc: Move dct{dp, qpq}, dr{sp, dpq}, dc{f, t}fix[q], dxex[q] "
` [PATCH v3 21/22] target/ppc: Move dct{dp,qpq},dr{sp,dpq},dc{f,t}fix[q],dxex[q] "
` [PATCH v3 22/22] target/ppc: Move ddedpd[q], denbcd[q], dscli[q], dscri[q] "
` [PATCH v3 22/22] target/ppc: Move ddedpd[q],denbcd[q],dscli[q],dscri[q] "
[PATCH v15 0/8] RISC-V Pointer Masking implementation
2021-10-21 22:56 UTC (2+ messages)
[gdbstub] redirecting qemu console output to a debugger
2021-10-21 22:08 UTC (4+ messages)
[PULL 0/1] Block patches
2021-10-21 22:08 UTC (2+ messages)
[PATCH v1 1/9] hw/riscv: opentitan: Update to the latest build
2021-10-21 21:58 UTC (4+ messages)
` [PATCH v1 5/9] hw/intc: sifive_plic: Cleanup the irq_request function
[PATCH] multiboot: Use DMA instead port-based transfer
2021-10-21 21:55 UTC (3+ messages)
[PATCH v2 0/6] hw/riscv: Use MachineState::ram and MachineClass::default_ram_id in all machines
2021-10-21 21:58 UTC (2+ messages)
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