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Thu, 19 Sep 2019 14:32:53 GMT Received: from userv0121.oracle.com (userv0121.oracle.com [156.151.31.72]) by aserp3020.oracle.com with ESMTP id 2v3vbg7mt3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 19 Sep 2019 14:32:53 +0000 Received: from abhmp0014.oracle.com (abhmp0014.oracle.com [141.146.116.20]) by userv0121.oracle.com (8.14.4/8.13.8) with ESMTP id x8JEWped002779; Thu, 19 Sep 2019 14:32:52 GMT Received: from [192.168.14.112] (/79.183.239.52) by default (Oracle Beehive Gateway v4.0) with ESMTP ; Thu, 19 Sep 2019 07:32:51 -0700 Content-Type: text/plain; charset=utf-8 Mime-Version: 1.0 (Mac OS X Mail 11.1 \(3445.4.7\)) Subject: Re: [PATCH 6/7] target/i386: add VMX features From: Liran Alon In-Reply-To: <1568716480-9973-7-git-send-email-pbonzini@redhat.com> Date: Thu, 19 Sep 2019 17:32:48 +0300 Content-Transfer-Encoding: quoted-printable Message-Id: References: <1568716480-9973-1-git-send-email-pbonzini@redhat.com> <1568716480-9973-7-git-send-email-pbonzini@redhat.com> To: Paolo Bonzini X-Mailer: Apple Mail (2.3445.4.7) X-Proofpoint-Virus-Version: vendor=nai engine=6000 definitions=9385 signatures=668685 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 suspectscore=0 malwarescore=0 phishscore=0 bulkscore=0 spamscore=0 mlxscore=0 mlxlogscore=678 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1908290000 definitions=main-1909190136 X-Proofpoint-Virus-Version: vendor=nai engine=6000 definitions=9385 signatures=668685 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1011 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=749 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1908290000 definitions=main-1909190137 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] X-Received-From: 156.151.31.86 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, ehabkost@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" > On 17 Sep 2019, at 13:34, Paolo Bonzini wrote: >=20 > Add code to convert the VMX feature words back into MSR values, > allowing the user to enable/disable VMX features as they wish. The = same > infrastructure enables support for limiting VMX features in named > CPU models. >=20 > Signed-off-by: Paolo Bonzini > --- > +static uint64_t make_vmx_msr_value(uint32_t index, uint32_t features) > +{ > + uint32_t default1, can_be_one, can_be_zero; > + uint32_t must_be_one; > + > + switch (index) { > + case MSR_IA32_VMX_TRUE_PINBASED_CTLS: > + default1 =3D 0x00000016; > + break; > + case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: > + default1 =3D 0x0401e172; > + break; > + case MSR_IA32_VMX_TRUE_ENTRY_CTLS: > + default1 =3D 0x000011ff; > + break; > + case MSR_IA32_VMX_TRUE_EXIT_CTLS: > + default1 =3D 0x00036dff; > + break; > + case MSR_IA32_VMX_PROCBASED_CTLS2: > + default1 =3D 0; > + break; > + default: > + abort(); > + } > + See below. > + /* > + * Bits 0-30, 32-44 and 50-53 come from the host. KVM should > + * not change them for backwards compatibility. > + */ > + uint64_t fixed_vmx_basic =3D kvm_vmx_basic & = 0x003c1fff7fffffffULL; > + > + /* > + * Same for bits 0-4 and 25-27. Bits 16-24 (CR3 target count) = can > + * change in the future but are always zero for now, clear them = to be > + * future proof. Bits 32-63 in theory could change, though KVM = does > + * not support dual-monitor treatment and probably never will; = mask > + * them out as well. > + */ > + uint64_t fixed_vmx_misc =3D kvm_vmx_misc & 0x0e00001f; I haven=E2=80=99t yet read deeply entire patch-series but I=E2=80=99m = definitely against having these hard-coded values in code instead of explicitly building proper = bitmap with well-defined bit names. This is error-prone and less readable. (E.g. Am I suppose as a reader to convert 0x0401e172 to which = processor-based controls it represents?) -Liran