From: Robert Henry <robhenry@microsoft.com>
To: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Subject: ia-32/ia-64 fxsave64 instruction behavior when saving mmx
Date: Fri, 29 May 2020 17:38:18 +0000 [thread overview]
Message-ID: <BL0PR2101MB1026B7400F5A568C9D5FC9DBD68F0@BL0PR2101MB1026.namprd21.prod.outlook.com> (raw)
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Background: The ia-32/ia-64 fxsave64 instruction saves fp80 or legacy SSE mmx registers. The mmx registers are saved as if they were fp80 values. The lower 64 bits of the constructed fp80 value is the mmx register. The upper 16 bits of the constructed fp80 value are reserved; see the last row of table 3-44 of https://www.felixcloutier.com/x86/fxsave#tbl-3-44
The Intel core i9-9980XE Skylake metal I have puts 0xffff into these reserved 16 bits when saving MMX.
QEMU appears to put 0's there.
Does anybody have insight as to what "reserved" really means, or must be, in this case? I take the verb "reserved" to mean something other than "undefined".
I came across this issue when running the remill instruction test engine. See my issue https://github.com/lifting-bits/remill/issues/423 For better or worse, remill assumes that those bits are 0xffff, not 0x0000
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next reply other threads:[~2020-05-29 17:54 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-29 17:38 Robert Henry [this message]
2020-05-31 23:22 ` ia-32/ia-64 fxsave64 instruction behavior when saving mmx Robert Henry
2020-06-01 6:19 ` Philippe Mathieu-Daudé
2020-07-31 20:34 ` Eduardo Habkost
2020-07-31 21:19 ` [EXTERNAL] " Robert Henry
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