RE: [PATCH v2 01/21] Hexagon (target/hexagon) TCG generation cleanup

From: Taylor Simpson <tsimpson@quicinc.com>
To: Richard Henderson <richard.henderson@linaro.org>,
	"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Cc: "ale@rev.ng" <ale@rev.ng>, Brian Cain <bcain@quicinc.com>,
	"philmd@redhat.com" <philmd@redhat.com>
Subject: RE: [PATCH v2 01/21] Hexagon (target/hexagon) TCG generation cleanup
Date: Fri, 2 Apr 2021 19:42:17 +0000	[thread overview]
Message-ID: <BYAPR02MB48860C83CC91FDFC9D9DC06DDE7A9@BYAPR02MB4886.namprd02.prod.outlook.com> (raw)
In-Reply-To: <0cbf66d0-e306-972a-ca39-aadae2e9dc27@linaro.org>

> -----Original Message-----
> From: Richard Henderson <richard.henderson@linaro.org>
> Sent: Friday, April 2, 2021 12:47 PM
> To: Taylor Simpson <tsimpson@quicinc.com>; qemu-devel@nongnu.org
> Cc: philmd@redhat.com; ale@rev.ng; Brian Cain <bcain@quicinc.com>
> Subject: Re: [PATCH v2 01/21] Hexagon (target/hexagon) TCG generation
> cleanup
>
> On 3/31/21 8:53 PM, Taylor Simpson wrote:
> > Simplify TCG generation of hex_reg_written
> >
> > Suggested-by: Richard Henderson <richard.henderson@linaro.org>
> > Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
> > ---
> >   target/hexagon/genptr.c | 14 +++++++++-----
> >   1 file changed, 9 insertions(+), 5 deletions(-)
> >
> > diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
> > index 7481f4c..87f5d92 100644
> > --- a/target/hexagon/genptr.c
> > +++ b/target/hexagon/genptr.c
> > @@ -35,7 +35,6 @@ static inline TCGv gen_read_preg(TCGv pred, uint8_t
> num)
> >
> >   static inline void gen_log_predicated_reg_write(int rnum, TCGv val, int
> slot)
> >   {
> > -    TCGv one = tcg_const_tl(1);
> >       TCGv zero = tcg_const_tl(0);
> >       TCGv slot_mask = tcg_temp_new();
> >
> > @@ -43,12 +42,17 @@ static inline void gen_log_predicated_reg_write(int
> rnum, TCGv val, int slot)
> >       tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum],
> slot_mask, zero,
> >                              val, hex_new_value[rnum]);
> >   #if HEX_DEBUG
> > -    /* Do this so HELPER(debug_commit_end) will know */
> > -    tcg_gen_movcond_tl(TCG_COND_EQ, hex_reg_written[rnum],
> slot_mask, zero,
> > -                       one, hex_reg_written[rnum]);
> > +    /*
> > +     * Do this so HELPER(debug_commit_end) will know
> > +     *
> > +     * Note that slot_mask indicates the value is not written
> > +     * (i.e., slot was cancelled), so we create a true/false value before
> > +     * or'ing with hex_reg_written[rnum].
> > +     */
> > +    tcg_gen_setcond_tl(TCG_COND_EQ, slot_mask, slot_mask, zero);
> > +    tcg_gen_or_tl(hex_reg_written[rnum], hex_reg_written[rnum],
> slot_mask);
> >   #endif
>
> Having looked forward at patch 5, it appears this could be further improved
> by examining ctx->regs_written.

It's not obvious how.  This is for a predicated instruction (e.g., if (p0) r2 = add(r1, r0)), so the checks need to be made at runtime.  There can be more than one predicated instruction in a packet that writes to the same register as long as only one of the predicates is true at runtime.

Am I missing something?

Thanks,
Taylor