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Tsirkin" Content-Type: multipart/alternative; boundary="00000000000049821905a45c7d71" Received-SPF: none client-ip=2a00:1450:4864:20::442; envelope-from=ani@anisinha.ca; helo=mail-wr1-x442.google.com X-detected-operating-system: by eggs.gnu.org: Error: [-] PROGRAM ABORT : Malformed IPv6 address (bad octet value). Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2a00:1450:4864:20::442 X-Mailman-Approved-At: Tue, 28 Apr 2020 13:34:12 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ani Sinha , Eduardo Habkost , qemu-devel@nongnu.org, Aleksandar Markovic , Paolo Bonzini , Igor Mammedov , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --00000000000049821905a45c7d71 Content-Type: text/plain; charset="UTF-8" On Tue, Apr 28, 2020 at 9:51 PM Michael S. Tsirkin wrote: > On Tue, Apr 28, 2020 at 09:39:16PM +0530, Ani Sinha wrote: > > > > Ani > > On Apr 28, 2020, 21:35 +0530, Michael S. Tsirkin , > wrote: > > > > On Tue, Apr 28, 2020 at 10:16:52AM +0000, Ani Sinha wrote: > > > > A new option "use_acpi_unplug" is introduced for PIIX which will > > selectively only disable hot unplugging of both hot plugged and > > cold plugged PCI devices on non-root PCI buses. This will prevent > > hot unplugging of devices from Windows based guests from system > > tray but will not prevent devices from being hot plugged into the > > guest. > > > > It has been tested on Windows guests. > > > > Signed-off-by: Ani Sinha > > > > > > It's still a non starter until we find something similar for PCIE and > > SHPC. Do guests check command status? Can some unplug commands fail? > > > > > > Ok I give up! I thought we debated this on the other thread. > > Sorry to hear that. > I'd rather you didn't, and worked on a solution that works for everyone. That is extremely hard for one person to do, without inputs and ideas from the community. Satisfying the entire world requires lot of time and energy investment, not to mention a broad expertise in multiple technologies. > Pushing back on merging code is unfortunately the only mechanism > maintainers have to make sure features are complete and > orthogonal to each other, so I'm not sure I can help otherwise. > > > > > > > > > > > --- > > hw/acpi/piix4.c | 3 +++ > > hw/i386/acpi-build.c | 40 > ++++++++++++++++++++++++++-------------- > > 2 files changed, 29 insertions(+), 14 deletions(-) > > > > diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c > > index 964d6f5..59fa707 100644 > > --- a/hw/acpi/piix4.c > > +++ b/hw/acpi/piix4.c > > @@ -78,6 +78,7 @@ typedef struct PIIX4PMState { > > > > AcpiPciHpState acpi_pci_hotplug; > > bool use_acpi_pci_hotplug; > > + bool use_acpi_unplug; > > > > uint8_t disable_s3; > > uint8_t disable_s4; > > @@ -633,6 +634,8 @@ static Property piix4_pm_properties[] = { > > DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2), > > DEFINE_PROP_BOOL("acpi-pci-hotplug-with-bridge-support", > PIIX4PMState, > > use_acpi_pci_hotplug, true), > > + DEFINE_PROP_BOOL("acpi-pci-hotunplug-enable-bridge", > PIIX4PMState, > > + use_acpi_unplug, true), > > DEFINE_PROP_BOOL("memory-hotplug-support", PIIX4PMState, > > acpi_memory_hotplug.is_enabled, true), > > DEFINE_PROP_END_OF_LIST(), > > diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c > > index 23c77ee..71b3ac3 100644 > > --- a/hw/i386/acpi-build.c > > +++ b/hw/i386/acpi-build.c > > @@ -96,6 +96,7 @@ typedef struct AcpiPmInfo { > > bool s3_disabled; > > bool s4_disabled; > > bool pcihp_bridge_en; > > + bool pcihup_bridge_en; > > uint8_t s4_val; > > AcpiFadtData fadt; > > uint16_t cpu_hp_io_base; > > @@ -240,6 +241,9 @@ static void acpi_get_pm_info(MachineState > *machine, > > AcpiPmInfo *pm) > > pm->pcihp_bridge_en = > > object_property_get_bool(obj, > "acpi-pci-hotplug-with-bridge-support", > > NULL); > > + pm->pcihup_bridge_en = > > + object_property_get_bool(obj, > "acpi-pci-hotunplug-enable-bridge", > > + NULL); > > } > > > > static void acpi_get_misc_info(AcpiMiscInfo *info) > > @@ -451,7 +455,8 @@ static void > build_append_pcihp_notify_entry(Aml > > *method, int slot) > > } > > > > static void build_append_pci_bus_devices(Aml *parent_scope, > PCIBus > > *bus, > > - bool pcihp_bridge_en) > > + bool pcihp_bridge_en, > > + bool pcihup_bridge_en) > > { > > Aml *dev, *notify_method = NULL, *method; > > QObject *bsel; > > @@ -479,11 +484,14 @@ static void > build_append_pci_bus_devices(Aml > > *parent_scope, PCIBus *bus, > > dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); > > aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); > > aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); > > - method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); > > - aml_append(method, > > - aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) > > - ); > > - aml_append(dev, method); > > + if (pcihup_bridge_en || pci_bus_is_root(bus)) { > > + method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); > > + aml_append(method, > > + aml_call2("PCEJ", aml_name("BSEL"), > > + aml_name("_SUN")) > > + ); > > + aml_append(dev, method); > > + } > > aml_append(parent_scope, dev); > > > > build_append_pcihp_notify_entry(notify_method, slot); > > @@ -537,12 +545,14 @@ static void > build_append_pci_bus_devices(Aml > > *parent_scope, PCIBus *bus, > > /* add _SUN/_EJ0 to make slot hotpluggable */ > > aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); > > > > - method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); > > - aml_append(method, > > - aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) > > - ); > > - aml_append(dev, method); > > - > > + if (pcihup_bridge_en || pci_bus_is_root(bus)) { > > + method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); > > + aml_append(method, > > + aml_call2("PCEJ", aml_name("BSEL"), > > + aml_name("_SUN")) > > + ); > > + aml_append(dev, method); > > + } > > if (bsel) { > > build_append_pcihp_notify_entry(notify_method, slot); > > } > > @@ -553,7 +563,8 @@ static void build_append_pci_bus_devices(Aml > > *parent_scope, PCIBus *bus, > > */ > > PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); > > > > - build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en); > > + build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en, > > + pcihup_bridge_en); > > } > > /* slot descriptor has been composed, add it into parent context > */ > > aml_append(parent_scope, dev); > > @@ -2196,7 +2207,8 @@ build_dsdt(GArray *table_data, BIOSLinker > > *linker, > > if (bus) { > > Aml *scope = aml_scope("PCI0"); > > /* Scan all PCI buses. Generate tables to support hotplug. */ > > - build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en); > > + build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en, > > + pm->pcihup_bridge_en); > > > > if (TPM_IS_TIS_ISA(tpm)) { > > if (misc->tpm_version == TPM_VERSION_2_0) { > > -- > > 1.9.4 > > > > > > > > --00000000000049821905a45c7d71 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


On Tue, Apr 28, 2020 at 9:51 PM Michael S. Tsirkin <mst@redhat.com> wrote:
On Tue, Apr 28, 2020 at 09:39:16PM +0530, Ani Sinh= a wrote:
>
> Ani
> On Apr 28, 2020, 21:35 +0530, Michael S. Tsirkin <mst@redhat.com>, wrote:
>
>=C2=A0 =C2=A0 =C2=A0On Tue, Apr 28, 2020 at 10:16:52AM +0000, Ani Sinha= wrote:
>
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0A new option "use_acpi_unplug&qu= ot; is introduced for PIIX which will
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0selectively only disable hot unpluggi= ng of both hot plugged and
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0cold plugged PCI devices on non-root = PCI buses. This will prevent
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0hot unplugging of devices from Window= s based guests from system
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0tray but will not prevent devices fro= m being hot plugged into the
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0guest.
>
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0It has been tested on Windows guests.=
>
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Signed-off-by: Ani Sinha <ani.sinha@nutanix.com>
>
>
>=C2=A0 =C2=A0 =C2=A0It's still a non starter until we find somethin= g similar for PCIE and
>=C2=A0 =C2=A0 =C2=A0SHPC. Do guests check command status? Can some unpl= ug commands fail?
>
>
> Ok I=C2=A0 give up! I thought we debated this on the other thread.

Sorry to hear that.
I'd rather you didn't, and worked on a solution that works for ever= yone.

That is ext= remely hard for one person to do, without inputs and ideas from the communi= ty. Satisfying the entire world requires lot of time and energy investment,= not to mention a broad expertise in multiple technologies.=C2=A0


Pushing back on merging code is unfortunately the only mechanism
maintainers have to make sure features are complete and
orthogonal to each other, so I'm not sure I can help otherwise.

>
>
>
>
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0---
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0hw/acpi/piix4.c | 3 +++
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0hw/i386/acpi-build.c | 40 +++++++++++= +++++++++++++++--------------
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A02 files changed, 29 insertions(+), 14= deletions(-)
>
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0diff --git a/hw/acpi/piix4.c b/hw/acp= i/piix4.c
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0index 964d6f5..59fa707 100644
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0--- a/hw/acpi/piix4.c
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0+++ b/hw/acpi/piix4.c
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0@@ -78,6 +78,7 @@ typedef struct PIIX= 4PMState {
>
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0AcpiPciHpState acpi_pci_hotplug;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0bool use_acpi_pci_hotplug;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0+ bool use_acpi_unplug;
>
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint8_t disable_s3;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint8_t disable_s4;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0@@ -633,6 +634,8 @@ static Property p= iix4_pm_properties[] =3D {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL= , PIIX4PMState, s4_val, 2),
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0DEFINE_PROP_BOOL("acpi-pci-hotpl= ug-with-bridge-support", PIIX4PMState,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0use_acpi_pci_hotplug, true),
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0+ DEFINE_PROP_BOOL("acpi-pci-hot= unplug-enable-bridge", PIIX4PMState,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0+ use_acpi_unplug, true),
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0DEFINE_PROP_BOOL("memory-hotplug= -support", PIIX4PMState,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0acpi_memory_hotplug.is_enabled, true)= ,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0DEFINE_PROP_END_OF_LIST(),
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0diff --git a/hw/i386/acpi-build.c b/h= w/i386/acpi-build.c
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0index 23c77ee..71b3ac3 100644
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0--- a/hw/i386/acpi-build.c
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0+++ b/hw/i386/acpi-build.c
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0@@ -96,6 +96,7 @@ typedef struct Acpi= PmInfo {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0bool s3_disabled;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0bool s4_disabled;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0bool pcihp_bridge_en;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0+ bool pcihup_bridge_en;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint8_t s4_val;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0AcpiFadtData fadt;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint16_t cpu_hp_io_base;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0@@ -240,6 +241,9 @@ static void acpi_= get_pm_info(MachineState *machine,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0AcpiPmInfo *pm)
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0pm->pcihp_bridge_en =3D
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0object_property_get_bool(obj, "a= cpi-pci-hotplug-with-bridge-support",
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0NULL);
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0+ pm->pcihup_bridge_en =3D
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0+ object_property_get_bool(obj, "= ;acpi-pci-hotunplug-enable-bridge",
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0+ NULL);
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}
>
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0static void acpi_get_misc_info(AcpiMi= scInfo *info)
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0@@ -451,7 +455,8 @@ static void build= _append_pcihp_notify_entry(Aml
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0*method, int slot)
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}
>
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0static void build_append_pci_bus_devi= ces(Aml *parent_scope, PCIBus
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0*bus,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0- bool pcihp_bridge_en)
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0+ bool pcihp_bridge_en,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0+ bool pcihup_bridge_en)
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0{
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Aml *dev, *notify_method =3D NULL, *m= ethod;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0QObject *bsel;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0@@ -479,11 +484,14 @@ static void bui= ld_append_pci_bus_devices(Aml
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0*parent_scope, PCIBus *bus,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0dev =3D aml_device("S%.02X"= , PCI_DEVFN(slot, 0));
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0aml_append(dev, aml_name_decl("_= SUN", aml_int(slot)));
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0aml_append(dev, aml_name_decl("_= ADR", aml_int(slot << 16)));
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0- method =3D aml_method("_EJ0&qu= ot;, 1, AML_NOTSERIALIZED);
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0- aml_append(method,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0- aml_call2("PCEJ", aml_nam= e("BSEL"), aml_name("_SUN"))
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0- );
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0- aml_append(dev, method);
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0+ if (pcihup_bridge_en || pci_bus_is_= root(bus)) {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0+ method =3D aml_method("_EJ0&qu= ot;, 1, AML_NOTSERIALIZED);
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0+ aml_append(method,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0+ aml_call2("PCEJ", aml_nam= e("BSEL"),
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0+ aml_name("_SUN"))
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0+ );
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0+ aml_append(dev, method);
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0+ }
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0aml_append(parent_scope, dev);
>
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0build_append_pcihp_notify_entry(notif= y_method, slot);
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0@@ -537,12 +545,14 @@ static void bui= ld_append_pci_bus_devices(Aml
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0*parent_scope, PCIBus *bus,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* add _SUN/_EJ0 to make slot hotplug= gable */
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0aml_append(dev, aml_name_decl("_= SUN", aml_int(slot)));
>
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0- method =3D aml_method("_EJ0&qu= ot;, 1, AML_NOTSERIALIZED);
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0- aml_append(method,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0- aml_call2("PCEJ", aml_nam= e("BSEL"), aml_name("_SUN"))
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0- );
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0- aml_append(dev, method);
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0-
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0+ if (pcihup_bridge_en || pci_bus_is_= root(bus)) {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0+ method =3D aml_method("_EJ0&qu= ot;, 1, AML_NOTSERIALIZED);
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0+ aml_append(method,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0+ aml_call2("PCEJ", aml_nam= e("BSEL"),
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0+ aml_name("_SUN"))
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0+ );
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0+ aml_append(dev, method);
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0+ }
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (bsel) {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0build_append_pcihp_notify_entry(notif= y_method, slot);
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0@@ -553,7 +563,8 @@ static void build= _append_pci_bus_devices(Aml
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0*parent_scope, PCIBus *bus,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0*/
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0PCIBus *sec_bus =3D pci_bridge_get_se= c_bus(PCI_BRIDGE(pdev));
>
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0- build_append_pci_bus_devices(dev, s= ec_bus, pcihp_bridge_en);
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0+ build_append_pci_bus_devices(dev, s= ec_bus, pcihp_bridge_en,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0+ pcihup_bridge_en);
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* slot descriptor has been composed,= add it into parent context */
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0aml_append(parent_scope, dev);
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0@@ -2196,7 +2207,8 @@ build_dsdt(GArr= ay *table_data, BIOSLinker
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0*linker,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (bus) {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Aml *scope =3D aml_scope("PCI0&q= uot;);
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* Scan all PCI buses. Generate table= s to support hotplug. */
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0- build_append_pci_bus_devices(scope,= bus, pm->pcihp_bridge_en);
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0+ build_append_pci_bus_devices(scope,= bus, pm->pcihp_bridge_en,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0+ pm->pcihup_bridge_en);
>
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (TPM_IS_TIS_ISA(tpm)) {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (misc->tpm_version =3D=3D TPM_V= ERSION_2_0) {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0--
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A01.9.4
>
>
>

--00000000000049821905a45c7d71--