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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Huacai Chen , Aleksandar Markovic , Aleksandar Rikalo , Aurelien Jarno , QEMU Developers Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Hi, Philippe, On Fri, Oct 16, 2020 at 11:15 PM Philippe Mathieu-Daud=C3=A9 wrote: > > On 10/16/20 8:51 AM, Huacai Chen wrote: > > From: Jiaxun Yang > > > > Our current code assumed the target page size is always 4k > > when handling PageMask and VPN2, however, variable page size > > was just added to mips target and that's no longer true. > > > > Fixes: ee3863b9d414 ("target/mips: Support variable page size") > > Signed-off-by: Jiaxun Yang > > Signed-off-by: Huacai Chen > > --- > > target/mips/cp0_helper.c | 36 +++++++++++++++++++++++++++++------- > > target/mips/cpu.h | 1 + > > 2 files changed, 30 insertions(+), 7 deletions(-) > > > > diff --git a/target/mips/cp0_helper.c b/target/mips/cp0_helper.c > > index de64add038..f3478d826b 100644 > > --- a/target/mips/cp0_helper.c > > +++ b/target/mips/cp0_helper.c > > @@ -867,13 +867,35 @@ void helper_mtc0_memorymapid(CPUMIPSState *env, t= arget_ulong arg1) > > > > void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *p= agemask) > > { > > - uint64_t mask =3D arg1 >> (TARGET_PAGE_BITS + 1); > > - if (!(env->insn_flags & ISA_MIPS32R6) || (arg1 =3D=3D ~0) || > > - (mask =3D=3D 0x0000 || mask =3D=3D 0x0003 || mask =3D=3D 0x000= F || > > - mask =3D=3D 0x003F || mask =3D=3D 0x00FF || mask =3D=3D 0x03F= F || > > - mask =3D=3D 0x0FFF || mask =3D=3D 0x3FFF || mask =3D=3D 0xFFF= F)) { > > - env->CP0_PageMask =3D arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK <= < 1)); > > + unsigned long mask; > > + int maskbits; > > + > > + if (env->insn_flags & ISA_MIPS32R6) { > > + return; > > + } > > + /* Don't care MASKX as we don't support 1KB page */ > > + mask =3D extract32((uint32_t)arg1, CP0PM_MASK, 16); > > + maskbits =3D find_first_zero_bit(&mask, 32); > > + > > + /* Ensure no more set bit after first zero */ > > + if (mask >> maskbits) { > > + goto invalid; > > + } > > + /* We don't support VTLB entry smaller than target page */ > > + if ((maskbits + 12) < TARGET_PAGE_BITS) { > > + goto invalid; > > } > > + env->CP0_PageMask =3D mask << CP0PM_MASK; > > + > > + return; > > + > > +invalid: > > + /* > > + * When invalid, ensure the value is bigger than or equal to > > + * the minimal but smaller than or equal to the maxium. > > + */ > > + maskbits =3D MIN(16, MAX(maskbits, TARGET_PAGE_BITS - 12)); > > + env->CP0_PageMask =3D ((1 << (16 + 1)) - 1) << CP0PM_MASK; > > } > > > > void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1) > > @@ -1104,7 +1126,7 @@ void helper_mthc0_saar(CPUMIPSState *env, target_= ulong arg1) > > void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1) > > { > > target_ulong old, val, mask; > > - mask =3D (TARGET_PAGE_MASK << 1) | env->CP0_EntryHi_ASID_mask; > > + mask =3D ~((1 << 14) - 1) | env->CP0_EntryHi_ASID_mask; > > if (((env->CP0_Config4 >> CP0C4_IE) & 0x3) >=3D 2) { > > mask |=3D 1 << CP0EnHi_EHINV; > > } > > diff --git a/target/mips/cpu.h b/target/mips/cpu.h > > index 7cf7f5239f..9c8bb23807 100644 > > --- a/target/mips/cpu.h > > +++ b/target/mips/cpu.h > > @@ -618,6 +618,7 @@ struct CPUMIPSState { > > * CP0 Register 5 > > */ > > int32_t CP0_PageMask; > > +#define CP0PM_MASK 13 > > int32_t CP0_PageGrain_rw_bitmask; > > int32_t CP0_PageGrain; > > #define CP0PG_RIE 31 > > > > Malta test failing: > > [ 0.000000] Linux version 4.5.0-2-4kc-malta > (debian-kernel@lists.debian.org) (gcc version 5.3.1 20160519 (Debian > 5.3.1-20) ) #1 Debian 4.5.5-1 (2016-05-29) > [ 0.000000] earlycon: Early serial console at I/O port 0x3f8 (options > '38400n8') > [ 0.000000] bootconsole [uart0] enabled > [ 0.000000] CPU0 revision is: 00019300 (MIPS 24Kc) > [ 0.000000] FPU revision is: 00739300 > [ 0.000000] MIPS: machine is mti,malta > [...] > Freeing unused kernel memory: 412K (80979000 - 809e0000) > do_page_fault(): sending SIGSEGV to mount for invalid write access to > 0018a000 > epc =3D 77848a54 in libc-2.27.so[7782f000+177000] > ra =3D 779d0618 in ld-2.27.so[779bf000+24000] > do_page_fault(): sending SIGSEGV to ln for invalid write access to 0018a0= 00 > epc =3D 778d4a54 in libc-2.27.so[778bb000+177000] > ra =3D 77a5c618 in ld-2.27.so[77a4b000+24000] > do_page_fault(): sending SIGSEGV to S01logging for invalid write access > to 0018a000 > epc =3D 77d08a54 in libc-2.27.so[77cef000+177000] > ra =3D 77e90618 in ld-2.27.so[77e7f000+24000] > do_page_fault(): sending SIGSEGV to S20urandom for invalid write access > to 0018a000 > epc =3D 76ee4a54 in libc-2.27.so[76ecb000+177000] > ra =3D 7706c618 in ld-2.27.so[7705b000+24000] > do_page_fault(): sending SIGSEGV to ifup for invalid write access to > 0018a000 > epc =3D 77974a54 in libc-2.27.so[7795b000+177000] > ra =3D 77afc618 in ld-2.27.so[77aeb000+24000] > do_page_fault(): sending SIGSEGV to awk for invalid read access from > 00000000 > epc =3D 00000000 in busybox[400000+d8000] > ra =3D 77248110 in libc-2.27.so[770fb000+177000] > do_page_fault(): sending SIGSEGV to cat for invalid write access to 0018a= 000 > epc =3D 77484a54 in libc-2.27.so[7746b000+177000] > ra =3D 7760c618 in ld-2.27.so[775fb000+24000] > do_page_fault(): sending SIGSEGV to run.sh for invalid write access to > 0018a000 > epc =3D 76e88a54 in libc-2.27.so[76e6f000+177000] > ra =3D 77010618 in ld-2.27.so[76fff000+24000] > qemu-system-mips: terminating on signal 2 > > Please run the QEMU tests. OK, we are investigating. > > The easiest way is to push your series on GitLab. > > Regards, > > Phil.