From: Joel Stanley <joel@jms.id.au>
To: "Cédric Le Goater" <clg@kaod.org>
Cc: Andrew Jeffery <andrew@aj.id.au>,
Peter Maydell <peter.maydell@linaro.org>,
qemu-arm <qemu-arm@nongnu.org>,
Eddie James <eajames@linux.ibm.com>,
QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [PATCH v2 08/21] aspeed/sdhci: Fix reset sequence
Date: Tue, 25 Aug 2020 05:56:47 +0000 [thread overview]
Message-ID: <CACPK8Xep5-nUqDFwd_HbG9OjV+vrwS1t_WgPsJJQoh9HHeSf+Q@mail.gmail.com> (raw)
In-Reply-To: <20200819100956.2216690-9-clg@kaod.org>
On Wed, 19 Aug 2020 at 10:10, Cédric Le Goater <clg@kaod.org> wrote:
>
> BIT(0) of the ASPEED_SDHCI_INFO register is set by SW and polled until
> the bit is cleared by HW.
>
> Use the number of supported slots to define the default value of this
> register (The AST2600 eMMC Controller only has one). Fix the reset
> sequence by clearing automatically the RESET bit.
>
> Cc: Eddie James <eajames@linux.ibm.com>
> Fixes: 2bea128c3d0b ("hw/sd/aspeed_sdhci: New device")
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
> ---
> hw/sd/aspeed_sdhci.c | 14 ++++++++++++--
> 1 file changed, 12 insertions(+), 2 deletions(-)
>
> diff --git a/hw/sd/aspeed_sdhci.c b/hw/sd/aspeed_sdhci.c
> index 22cafce0fbdc..4f24b7d2f942 100644
> --- a/hw/sd/aspeed_sdhci.c
> +++ b/hw/sd/aspeed_sdhci.c
> @@ -16,7 +16,9 @@
> #include "hw/qdev-properties.h"
>
> #define ASPEED_SDHCI_INFO 0x00
> -#define ASPEED_SDHCI_INFO_RESET 0x00030000
> +#define ASPEED_SDHCI_INFO_SLOT1 (1 << 17)
> +#define ASPEED_SDHCI_INFO_SLOT0 (1 << 16)
> +#define ASPEED_SDHCI_INFO_RESET (1 << 0)
> #define ASPEED_SDHCI_DEBOUNCE 0x04
> #define ASPEED_SDHCI_DEBOUNCE_RESET 0x00000005
> #define ASPEED_SDHCI_BUS 0x08
> @@ -67,6 +69,10 @@ static void aspeed_sdhci_write(void *opaque, hwaddr addr, uint64_t val,
> AspeedSDHCIState *sdhci = opaque;
>
> switch (addr) {
> + case ASPEED_SDHCI_INFO:
> + /* The RESET bit automatically clears. */
> + sdhci->regs[TO_REG(addr)] = (uint32_t)val & ~ASPEED_SDHCI_INFO_RESET;
> + break;
> case ASPEED_SDHCI_SDIO_140:
> sdhci->slots[0].capareg = (uint64_t)(uint32_t)val;
> break;
> @@ -155,7 +161,11 @@ static void aspeed_sdhci_reset(DeviceState *dev)
> AspeedSDHCIState *sdhci = ASPEED_SDHCI(dev);
>
> memset(sdhci->regs, 0, ASPEED_SDHCI_REG_SIZE);
> - sdhci->regs[TO_REG(ASPEED_SDHCI_INFO)] = ASPEED_SDHCI_INFO_RESET;
> +
> + sdhci->regs[TO_REG(ASPEED_SDHCI_INFO)] = ASPEED_SDHCI_INFO_SLOT0;
> + if (sdhci->num_slots == 2) {
> + sdhci->regs[TO_REG(ASPEED_SDHCI_INFO)] |= ASPEED_SDHCI_INFO_SLOT1;
> + }
> sdhci->regs[TO_REG(ASPEED_SDHCI_DEBOUNCE)] = ASPEED_SDHCI_DEBOUNCE_RESET;
> }
>
> --
> 2.25.4
>
next prev parent reply other threads:[~2020-08-25 5:59 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-19 10:09 [PATCH v2 00/21] aspeed: cleanups and some extensions Cédric Le Goater
2020-08-19 10:09 ` [PATCH v2 01/21] m25p80: Return the JEDEC ID twice for mx25l25635e Cédric Le Goater
2020-08-19 10:09 ` [PATCH v2 02/21] m25p80: Add support for mx25l25635f Cédric Le Goater
2020-08-28 7:00 ` Cédric Le Goater
2020-08-19 10:09 ` [PATCH v2 03/21] m25p80: Add support for n25q512ax3 Cédric Le Goater
2020-08-19 10:09 ` [PATCH v2 04/21] aspeed/scu: Fix valid access size on AST2400 Cédric Le Goater
2020-08-19 10:09 ` [PATCH v2 05/21] hw/arm/aspeed: Add board model for Supermicro X11 BMC Cédric Le Goater
2020-08-25 14:33 ` Peter Maydell
2020-08-25 14:37 ` Erik Smit
2020-08-25 15:18 ` Peter Maydell
2020-08-28 6:16 ` Cédric Le Goater
2020-08-19 10:09 ` [PATCH v2 06/21] aspeed/smc: Fix MemoryRegionOps definition Cédric Le Goater
2020-08-19 10:09 ` [PATCH v2 07/21] aspeed/smc: Fix max_slaves of the legacy SMC device Cédric Le Goater
2020-08-19 10:09 ` [PATCH v2 08/21] aspeed/sdhci: Fix reset sequence Cédric Le Goater
2020-08-25 5:56 ` Joel Stanley [this message]
2020-08-19 10:09 ` [PATCH v2 09/21] ftgmac100: Fix registers that can be read Cédric Le Goater
2020-08-19 10:09 ` [PATCH v2 10/21] ftgmac100: Fix interrupt status "Packet transmitted on ethernet" Cédric Le Goater
2020-08-19 10:09 ` [PATCH v2 11/21] ftgmac100: Fix interrupt status "Packet moved to RX FIFO" Cédric Le Goater
2020-08-19 10:09 ` [PATCH v2 12/21] ftgmac100: Change interrupt status when a DMA error occurs Cédric Le Goater
2020-08-19 10:09 ` [PATCH v2 13/21] ftgmac100: Check for invalid len and address before doing a DMA transfer Cédric Le Goater
2020-08-19 10:09 ` [PATCH v2 14/21] ftgmac100: Fix integer overflow in ftgmac100_do_tx() Cédric Le Goater
2020-08-19 10:09 ` [PATCH v2 15/21] ftgmac100: Improve software reset Cédric Le Goater
2020-08-19 10:09 ` [PATCH v2 16/21] aspeed/sdmc: Perform memory training Cédric Le Goater
2020-08-19 10:09 ` [PATCH v2 17/21] aspeed/sdmc: Allow writes to unprotected registers Cédric Le Goater
2020-08-19 10:09 ` [PATCH v2 18/21] aspeed/sdmc: Simplify calculation of RAM bits Cédric Le Goater
2020-08-19 10:09 ` [PATCH v2 19/21] aspeed/smc: Open AHB window of the second chip of the AST2600 FMC controller Cédric Le Goater
2020-08-19 10:09 ` [PATCH v2 20/21] arm: aspeed: add strap define `25HZ` of AST2500 Cédric Le Goater
2020-08-19 10:09 ` [PATCH v2 21/21] hw: add a number of SPI-flash's of m25p80 family Cédric Le Goater
2020-08-25 6:01 ` [PATCH v2 00/21] aspeed: cleanups and some extensions Joel Stanley
2020-08-25 7:20 ` Cédric Le Goater
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=CACPK8Xep5-nUqDFwd_HbG9OjV+vrwS1t_WgPsJJQoh9HHeSf+Q@mail.gmail.com \
--to=joel@jms.id.au \
--cc=andrew@aj.id.au \
--cc=clg@kaod.org \
--cc=eajames@linux.ibm.com \
--cc=peter.maydell@linaro.org \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).