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From: Joel Stanley <joel@jms.id.au>
To: "Cédric Le Goater" <clg@kaod.org>
Cc: Andrew Jeffery <andrew@aj.id.au>,
	Peter Maydell <peter.maydell@linaro.org>,
	Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>,
	qemu-arm <qemu-arm@nongnu.org>,
	QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [PATCH 15/24] aspeed/smc: Add extra controls to request DMA
Date: Fri, 9 Apr 2021 06:54:49 +0000	[thread overview]
Message-ID: <CACPK8Xfk9dPXdtr=BZq+9yTrFSYg_pyTX+Gk8JbcomjwVpTmjw@mail.gmail.com> (raw)
In-Reply-To: <20210407171637.777743-16-clg@kaod.org>

On Wed, 7 Apr 2021 at 17:17, Cédric Le Goater <clg@kaod.org> wrote:
>
> The AST2600 SPI controllers have a set of bits to request/grant DMA
> access. Add a new SMC feature for these controllers and use it to
> check access to the DMA registers.

Ah this is why you added the features mask. Makes sense.

Reviewed-by: Joel Stanley <joel@jms.id.au>

>
> Cc: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
>  include/hw/ssi/aspeed_smc.h |  1 +
>  hw/ssi/aspeed_smc.c         | 74 +++++++++++++++++++++++++++++++++----
>  2 files changed, 68 insertions(+), 7 deletions(-)
>
> diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h
> index 07879fd1c4a7..cdaf165300b6 100644
> --- a/include/hw/ssi/aspeed_smc.h
> +++ b/include/hw/ssi/aspeed_smc.h
> @@ -55,6 +55,7 @@ typedef struct AspeedSMCController {
>                                 const AspeedSegments *seg);
>      void (*reg_to_segment)(const struct AspeedSMCState *s, uint32_t reg,
>                             AspeedSegments *seg);
> +    void (*dma_ctrl)(struct AspeedSMCState *s, uint32_t value);
>  } AspeedSMCController;
>
>  typedef struct AspeedSMCFlash {
> diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
> index 4521bbd4864e..189b35637c77 100644
> --- a/hw/ssi/aspeed_smc.c
> +++ b/hw/ssi/aspeed_smc.c
> @@ -127,6 +127,8 @@
>
>  /* DMA Control/Status Register */
>  #define R_DMA_CTRL        (0x80 / 4)
> +#define   DMA_CTRL_REQUEST      (1 << 31)
> +#define   DMA_CTRL_GRANT        (1 << 30)
>  #define   DMA_CTRL_DELAY_MASK   0xf
>  #define   DMA_CTRL_DELAY_SHIFT  8
>  #define   DMA_CTRL_FREQ_MASK    0xf
> @@ -228,6 +230,7 @@ static uint32_t aspeed_smc_segment_to_reg(const AspeedSMCState *s,
>                                            const AspeedSegments *seg);
>  static void aspeed_smc_reg_to_segment(const AspeedSMCState *s, uint32_t reg,
>                                        AspeedSegments *seg);
> +static void aspeed_smc_dma_ctrl(AspeedSMCState *s, uint32_t value);
>
>  /*
>   * AST2600 definitions
> @@ -257,7 +260,10 @@ static uint32_t aspeed_2600_smc_segment_to_reg(const AspeedSMCState *s,
>                                                 const AspeedSegments *seg);
>  static void aspeed_2600_smc_reg_to_segment(const AspeedSMCState *s,
>                                             uint32_t reg, AspeedSegments *seg);
> +static void aspeed_2600_smc_dma_ctrl(AspeedSMCState *s, uint32_t value);
> +
>  #define ASPEED_SMC_FEATURE_DMA       0x1
> +#define ASPEED_SMC_FEATURE_DMA_GRANT 0x2
>
>  static inline bool aspeed_smc_has_dma(const AspeedSMCState *s)
>  {
> @@ -281,6 +287,7 @@ static const AspeedSMCController controllers[] = {
>          .nregs             = ASPEED_SMC_R_SMC_MAX,
>          .segment_to_reg    = aspeed_smc_segment_to_reg,
>          .reg_to_segment    = aspeed_smc_reg_to_segment,
> +        .dma_ctrl          = aspeed_smc_dma_ctrl,
>      }, {
>          .name              = "aspeed.fmc-ast2400",
>          .r_conf            = R_CONF,
> @@ -299,6 +306,7 @@ static const AspeedSMCController controllers[] = {
>          .nregs             = ASPEED_SMC_R_MAX,
>          .segment_to_reg    = aspeed_smc_segment_to_reg,
>          .reg_to_segment    = aspeed_smc_reg_to_segment,
> +        .dma_ctrl          = aspeed_smc_dma_ctrl,
>      }, {
>          .name              = "aspeed.spi1-ast2400",
>          .r_conf            = R_SPI_CONF,
> @@ -315,6 +323,7 @@ static const AspeedSMCController controllers[] = {
>          .nregs             = ASPEED_SMC_R_SPI_MAX,
>          .segment_to_reg    = aspeed_smc_segment_to_reg,
>          .reg_to_segment    = aspeed_smc_reg_to_segment,
> +        .dma_ctrl          = aspeed_smc_dma_ctrl,
>      }, {
>          .name              = "aspeed.fmc-ast2500",
>          .r_conf            = R_CONF,
> @@ -333,6 +342,7 @@ static const AspeedSMCController controllers[] = {
>          .nregs             = ASPEED_SMC_R_MAX,
>          .segment_to_reg    = aspeed_smc_segment_to_reg,
>          .reg_to_segment    = aspeed_smc_reg_to_segment,
> +        .dma_ctrl          = aspeed_smc_dma_ctrl,
>      }, {
>          .name              = "aspeed.spi1-ast2500",
>          .r_conf            = R_CONF,
> @@ -349,6 +359,7 @@ static const AspeedSMCController controllers[] = {
>          .nregs             = ASPEED_SMC_R_MAX,
>          .segment_to_reg    = aspeed_smc_segment_to_reg,
>          .reg_to_segment    = aspeed_smc_reg_to_segment,
> +        .dma_ctrl          = aspeed_smc_dma_ctrl,
>      }, {
>          .name              = "aspeed.spi2-ast2500",
>          .r_conf            = R_CONF,
> @@ -365,6 +376,7 @@ static const AspeedSMCController controllers[] = {
>          .nregs             = ASPEED_SMC_R_MAX,
>          .segment_to_reg    = aspeed_smc_segment_to_reg,
>          .reg_to_segment    = aspeed_smc_reg_to_segment,
> +        .dma_ctrl          = aspeed_smc_dma_ctrl,
>      }, {
>          .name              = "aspeed.fmc-ast2600",
>          .r_conf            = R_CONF,
> @@ -383,6 +395,7 @@ static const AspeedSMCController controllers[] = {
>          .nregs             = ASPEED_SMC_R_MAX,
>          .segment_to_reg    = aspeed_2600_smc_segment_to_reg,
>          .reg_to_segment    = aspeed_2600_smc_reg_to_segment,
> +        .dma_ctrl          = aspeed_2600_smc_dma_ctrl,
>      }, {
>          .name              = "aspeed.spi1-ast2600",
>          .r_conf            = R_CONF,
> @@ -395,12 +408,14 @@ static const AspeedSMCController controllers[] = {
>          .segments          = aspeed_segments_ast2600_spi1,
>          .flash_window_base = ASPEED26_SOC_SPI_FLASH_BASE,
>          .flash_window_size = 0x10000000,
> -        .features          = ASPEED_SMC_FEATURE_DMA,
> +        .features          = ASPEED_SMC_FEATURE_DMA |
> +                             ASPEED_SMC_FEATURE_DMA_GRANT,
>          .dma_flash_mask    = 0x0FFFFFFC,
>          .dma_dram_mask     = 0x3FFFFFFC,
>          .nregs             = ASPEED_SMC_R_MAX,
>          .segment_to_reg    = aspeed_2600_smc_segment_to_reg,
>          .reg_to_segment    = aspeed_2600_smc_reg_to_segment,
> +        .dma_ctrl          = aspeed_2600_smc_dma_ctrl,
>      }, {
>          .name              = "aspeed.spi2-ast2600",
>          .r_conf            = R_CONF,
> @@ -413,12 +428,14 @@ static const AspeedSMCController controllers[] = {
>          .segments          = aspeed_segments_ast2600_spi2,
>          .flash_window_base = ASPEED26_SOC_SPI2_FLASH_BASE,
>          .flash_window_size = 0x10000000,
> -        .features          = ASPEED_SMC_FEATURE_DMA,
> +        .features          = ASPEED_SMC_FEATURE_DMA |
> +                             ASPEED_SMC_FEATURE_DMA_GRANT,
>          .dma_flash_mask    = 0x0FFFFFFC,
>          .dma_dram_mask     = 0x3FFFFFFC,
>          .nregs             = ASPEED_SMC_R_MAX,
>          .segment_to_reg    = aspeed_2600_smc_segment_to_reg,
>          .reg_to_segment    = aspeed_2600_smc_reg_to_segment,
> +        .dma_ctrl          = aspeed_2600_smc_dma_ctrl,
>      },
>  };
>
> @@ -1240,7 +1257,7 @@ static void aspeed_smc_dma_done(AspeedSMCState *s)
>      }
>  }
>
> -static void aspeed_smc_dma_ctrl(AspeedSMCState *s, uint64_t dma_ctrl)
> +static void aspeed_smc_dma_ctrl(AspeedSMCState *s, uint32_t dma_ctrl)
>  {
>      if (!(dma_ctrl & DMA_CTRL_ENABLE)) {
>          s->regs[R_DMA_CTRL] = dma_ctrl;
> @@ -1265,6 +1282,46 @@ static void aspeed_smc_dma_ctrl(AspeedSMCState *s, uint64_t dma_ctrl)
>      aspeed_smc_dma_done(s);
>  }
>
> +static inline bool aspeed_smc_dma_granted(AspeedSMCState *s)
> +{
> +    if (!(s->ctrl->features & ASPEED_SMC_FEATURE_DMA_GRANT)) {
> +        return true;
> +    }
> +
> +    if (!(s->regs[R_DMA_CTRL] & DMA_CTRL_GRANT)) {
> +        qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA not granted\n",  __func__);
> +        return false;
> +    }
> +
> +    return true;
> +}
> +
> +static void aspeed_2600_smc_dma_ctrl(AspeedSMCState *s, uint32_t dma_ctrl)
> +{
> +    /* Preserve DMA bits  */
> +    dma_ctrl |= s->regs[R_DMA_CTRL] & (DMA_CTRL_REQUEST | DMA_CTRL_GRANT);
> +
> +    if (dma_ctrl == 0xAEED0000) {
> +        /* automatically grant request */
> +        s->regs[R_DMA_CTRL] |= (DMA_CTRL_REQUEST | DMA_CTRL_GRANT);
> +        return;
> +    }
> +
> +    /* clear request */
> +    if (dma_ctrl == 0xDEEA0000) {
> +        s->regs[R_DMA_CTRL] &= ~(DMA_CTRL_REQUEST | DMA_CTRL_GRANT);
> +        return;
> +    }
> +
> +    if (!aspeed_smc_dma_granted(s)) {
> +        qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA not granted\n",  __func__);
> +        return;
> +    }
> +
> +    aspeed_smc_dma_ctrl(s, dma_ctrl);
> +    s->regs[R_DMA_CTRL] &= ~(DMA_CTRL_REQUEST | DMA_CTRL_GRANT);
> +}
> +
>  static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data,
>                               unsigned int size)
>  {
> @@ -1297,12 +1354,15 @@ static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data,
>      } else if (addr == R_INTR_CTRL) {
>          s->regs[addr] = value;
>      } else if (aspeed_smc_has_dma(s) && addr == R_DMA_CTRL) {
> -        aspeed_smc_dma_ctrl(s, value);
> -    } else if (aspeed_smc_has_dma(s) && addr == R_DMA_DRAM_ADDR) {
> +        s->ctrl->dma_ctrl(s, value);
> +    } else if (aspeed_smc_has_dma(s) && addr == R_DMA_DRAM_ADDR &&
> +               aspeed_smc_dma_granted(s)) {
>          s->regs[addr] = DMA_DRAM_ADDR(s, value);
> -    } else if (aspeed_smc_has_dma(s) && addr == R_DMA_FLASH_ADDR) {
> +    } else if (aspeed_smc_has_dma(s) && addr == R_DMA_FLASH_ADDR &&
> +               aspeed_smc_dma_granted(s)) {
>          s->regs[addr] = DMA_FLASH_ADDR(s, value);
> -    } else if (aspeed_smc_has_dma(s) && addr == R_DMA_LEN) {
> +    } else if (aspeed_smc_has_dma(s) && addr == R_DMA_LEN &&
> +               aspeed_smc_dma_granted(s)) {
>          s->regs[addr] = DMA_LENGTH(value);
>      } else {
>          qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n",
> --
> 2.26.3
>


  reply	other threads:[~2021-04-09  6:57 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-07 17:16 [PATCH 00/24] aspeed: fixes and extensions Cédric Le Goater
2021-04-07 17:16 ` [PATCH 01/24] aspeed/smc: Use the RAM memory region for DMAs Cédric Le Goater
2021-04-07 17:32   ` Philippe Mathieu-Daudé
2021-04-07 17:16 ` [PATCH 02/24] aspeed/smc: Remove unused "sdram-base" property Cédric Le Goater
2021-04-07 17:32   ` Philippe Mathieu-Daudé
2021-04-07 17:16 ` [PATCH 03/24] aspeed/i2c: Fix DMA address mask Cédric Le Goater
2021-04-07 21:22   ` Philippe Mathieu-Daudé
2021-04-08  8:58     ` Cédric Le Goater
2021-04-07 17:16 ` [PATCH 04/24] aspeed/i2c: Rename DMA address space Cédric Le Goater
2021-04-07 17:33   ` Philippe Mathieu-Daudé
2021-04-07 17:16 ` [PATCH 05/24] hw/arm/aspeed: Do not sysbus-map mmio flash region directly, use alias Cédric Le Goater
2021-04-07 17:16 ` [PATCH 06/24] hw: Model ASPEED's Hash and Crypto Engine Cédric Le Goater
2021-04-07 19:31   ` Klaus Heinrich Kiwi
2021-04-07 17:16 ` [PATCH 07/24] aspeed: Integrate HACE Cédric Le Goater
2021-04-07 19:22   ` Klaus Heinrich Kiwi
2021-04-07 17:16 ` [PATCH 08/24] tests/qtest: Add test for Aspeed HACE Cédric Le Goater
2021-04-07 19:33   ` Klaus Heinrich Kiwi
2021-04-07 17:16 ` [PATCH 09/24] aspeed: Add Scater-Gather support for HACE Hash Cédric Le Goater
2021-04-08 12:39   ` Joel Stanley
2021-04-07 17:16 ` [PATCH 10/24] tests: Aspeed HACE Scatter-Gather tests Cédric Le Goater
2021-04-07 17:16 ` [PATCH 11/24] tests/acceptance: Test ast2400 and ast2500 machines Cédric Le Goater
2021-04-07 18:40   ` Willian Rampazzo
2021-04-07 17:16 ` [PATCH 12/24] tests/acceptance: Test ast2600 machine Cédric Le Goater
2021-04-07 18:36   ` Willian Rampazzo
2021-04-07 17:16 ` [PATCH 13/24] hw/misc/aspeed_xdma: Add AST2600 support Cédric Le Goater
2021-04-07 20:29   ` Eddie James
2021-04-07 17:16 ` [PATCH 14/24] aspeed/smc: Add a 'features' attribute to the object class Cédric Le Goater
2021-04-09  6:55   ` Joel Stanley
2021-04-07 17:16 ` [PATCH 15/24] aspeed/smc: Add extra controls to request DMA Cédric Le Goater
2021-04-09  6:54   ` Joel Stanley [this message]
2021-04-10  7:08     ` Cédric Le Goater
2021-04-07 17:16 ` [PATCH 16/24] tests/qtest: Rename m25p80 test in aspeed_smc test Cédric Le Goater
2021-04-09  6:55   ` Joel Stanley
2021-04-07 17:16 ` [PATCH 17/24] aspeed: Remove swift-bmc machine Cédric Le Goater
2021-04-07 18:13   ` Adriana Kobylak
2021-04-07 18:29   ` Peter Maydell
2021-04-08  7:40     ` Cédric Le Goater
2021-04-08  9:05       ` Peter Maydell
2021-04-07 17:16 ` [PATCH 18/24] aspeed: Add support for the rainier-bmc board Cédric Le Goater
2021-04-09  6:57   ` Joel Stanley
2021-04-07 17:16 ` [PATCH 19/24] hw/misc: Add an iBT device model Cédric Le Goater
2021-04-07 17:16 ` [PATCH 20/24] aspeed: Emulate the AST2600A3 Cédric Le Goater
2021-04-07 17:16 ` [PATCH 21/24] hw/block: m25p80: Add support for mt25qu02g Cédric Le Goater
2021-04-07 17:36   ` Alistair Francis
2021-04-08  8:00   ` Francisco Iglesias
2021-04-08  8:40     ` Cédric Le Goater
2021-04-08  9:21       ` Francisco Iglesias
2021-04-07 17:16 ` [PATCH 22/24] hw/misc: Add Infineon DPS310 sensor model Cédric Le Goater
2021-04-07 17:16 ` [PATCH 23/24] arm/aspeed: Add DPS310 to rainier Cédric Le Goater
2021-04-07 17:16 ` [PATCH 24/24] arm/aspeed: Add DPS310 to witherspoon Cédric Le Goater

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