From: Dayeol Lee <dayeol@berkeley.edu>
To: Jonathan Behrens <fintelia@gmail.com>
Cc: "open list:RISC-V TCG CPUs" <qemu-riscv@nongnu.org>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Palmer Dabbelt <palmer@sifive.com>,
Richard Henderson <richard.henderson@linaro.org>,
qemu-devel@nongnu.org,
Alistair Francis <Alistair.Francis@wdc.com>,
diodesign@tuta.io
Subject: Re: [PATCH] target/riscv: PMP violation due to wrong size parameter
Date: Sat, 12 Oct 2019 11:30:25 -0700 [thread overview]
Message-ID: <CACjxMEsTuKEsL2OPVDGuUX8mCJCcOcLO1d0c3YFwmY1xxqP+Tg@mail.gmail.com> (raw)
In-Reply-To: <CANnJOVHy8TuitQHBQ=+uh6ZKB=5iEZaE2CsLosti5mHQvRi_KA@mail.gmail.com>
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No it doesn't mean that.
But the following code will make the size TARGET_PAGE_SIZE - (page offset)
if the address is not aligned.
pmp_size = -(address | TARGET_PAGE_MASK)
On Fri, Oct 11, 2019, 7:37 PM Jonathan Behrens <fintelia@gmail.com> wrote:
> How do you know that the access won't straddle a page boundary? Is there a
> guarantee somewhere that size=0 means that the access is naturally aligned?
>
> Jonathan
>
>
> On Fri, Oct 11, 2019 at 7:14 PM Dayeol Lee <dayeol@berkeley.edu> wrote:
>
>> riscv_cpu_tlb_fill() uses the `size` parameter to check PMP violation
>> using pmp_hart_has_privs().
>> However, if the size is unknown (=0), the ending address will be
>> `addr - 1` as it is `addr + size - 1` in `pmp_hart_has_privs()`.
>> This always causes a false PMP violation on the starting address of the
>> range, as `addr - 1` is not in the range.
>>
>> In order to fix, we just assume that all bytes from addr to the end of
>> the page will be accessed if the size is unknown.
>>
>> Signed-off-by: Dayeol Lee <dayeol@berkeley.edu>
>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>> target/riscv/cpu_helper.c | 13 ++++++++++++-
>> 1 file changed, 12 insertions(+), 1 deletion(-)
>>
>> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
>> index e32b6126af..7d9a22b601 100644
>> --- a/target/riscv/cpu_helper.c
>> +++ b/target/riscv/cpu_helper.c
>> @@ -441,6 +441,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address,
>> int size,
>> CPURISCVState *env = &cpu->env;
>> hwaddr pa = 0;
>> int prot;
>> + int pmp_size = 0;
>> bool pmp_violation = false;
>> int ret = TRANSLATE_FAIL;
>> int mode = mmu_idx;
>> @@ -460,9 +461,19 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address,
>> int size,
>> "%s address=%" VADDR_PRIx " ret %d physical "
>> TARGET_FMT_plx
>> " prot %d\n", __func__, address, ret, pa, prot);
>>
>> + /*
>> + * if size is unknown (0), assume that all bytes
>> + * from addr to the end of the page will be accessed.
>> + */
>> + if (size == 0) {
>> + pmp_size = -(address | TARGET_PAGE_MASK);
>> + } else {
>> + pmp_size = size;
>> + }
>> +
>> if (riscv_feature(env, RISCV_FEATURE_PMP) &&
>> (ret == TRANSLATE_SUCCESS) &&
>> - !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
>> + !pmp_hart_has_privs(env, pa, pmp_size, 1 << access_type, mode)) {
>> ret = TRANSLATE_PMP_FAIL;
>> }
>> if (ret == TRANSLATE_PMP_FAIL) {
>> --
>> 2.20.1
>>
>>
>>
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next prev parent reply other threads:[~2019-10-12 18:35 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-11 23:14 [PATCH] target/riscv: PMP violation due to wrong size parameter Dayeol Lee
2019-10-12 2:37 ` Jonathan Behrens
2019-10-12 18:30 ` Dayeol Lee [this message]
2019-10-15 17:04 ` Dayeol Lee
2019-10-18 19:01 ` Palmer Dabbelt
2019-10-18 19:28 ` Dayeol Lee
-- strict thread matches above, loose matches on Subject: below --
2019-10-22 21:21 Dayeol Lee
2019-10-23 15:50 ` Palmer Dabbelt
2019-10-07 5:28 Dayeol Lee
2019-10-07 6:20 ` no-reply
2019-10-07 13:00 ` Richard Henderson
2019-10-07 17:19 ` Dayeol Lee
2019-10-07 18:25 ` Richard Henderson
2019-10-07 18:41 ` Dayeol Lee
2019-10-08 3:18 ` Richard Henderson
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