From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <alistair23@gmail.com>
Cc: Bin Meng <bin.meng@windriver.com>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Palmer Dabbelt <palmerdabbelt@google.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Alistair Francis <Alistair.Francis@wdc.com>
Subject: Re: [PATCH v2 2/5] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004
Date: Thu, 18 Jun 2020 13:08:43 +0800 [thread overview]
Message-ID: <CAEUhbmU3ouNn=PfXLwZx_Pu49zmWY1ddsSqKONdh6X5atXcncg@mail.gmail.com> (raw)
In-Reply-To: <CAEUhbmVq8kVfZRQSF-LT_bDib9e1xBL-7zifmHpQgdvehcNzFA@mail.gmail.com>
Hi Alistair,
On Thu, Jun 18, 2020 at 8:41 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Hi Alistair,
>
> On Thu, Jun 18, 2020 at 12:40 AM Alistair Francis <alistair23@gmail.com> wrote:
> >
> > On Mon, Jun 15, 2020 at 5:51 PM Bin Meng <bmeng.cn@gmail.com> wrote:
> > >
> > > From: Bin Meng <bin.meng@windriver.com>
> > >
> > > Per the SiFive manual, all E/U series CPU cores' reset vector is
> > > at 0x1004. Update our codes to match the hardware.
> > >
> > > Signed-off-by: Bin Meng <bin.meng@windriver.com>
> >
> > This commit breaks my Oreboot test.
> >
> > Oreboot starts in flash and we run the command with the
> > `sifive_u,start-in-flash=true` machine.
>
> Could you please post an Oreboot binary for testing somewhere, or some
> instructions so that I can test this?
>
I have figured out where the issue is. The issue is inside the Oreboot
codes that its QEMU detecting logic should be updated to match this
change.
I've sent pull request to Oreboot to fix this:
https://github.com/oreboot/oreboot/pull/264
> >
> > I have removed this and the later patches from the RISC-V branch. I
> > want to send a PR today. After that I'll look into this.
>
I don't think we should drop this patch and later ones in this series.
Regards,
Bin
next prev parent reply other threads:[~2020-06-18 5:25 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-16 0:50 [PATCH v2 0/5] hw/riscv: sifive_u: Add Mode Select (MSEL[3:0]) support Bin Meng
2020-06-16 0:50 ` [PATCH v2 1/5] target/riscv: Rename IBEX CPU init routine Bin Meng
2020-06-16 17:07 ` Alistair Francis
2020-06-16 0:50 ` [PATCH v2 2/5] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004 Bin Meng
2020-06-16 17:09 ` Alistair Francis
2020-06-17 16:30 ` Alistair Francis
2020-06-18 0:41 ` Bin Meng
2020-06-18 5:08 ` Bin Meng [this message]
2020-06-19 6:04 ` Alistair Francis
2020-06-16 0:50 ` [PATCH v2 3/5] hw/riscv: sifive_u: Support different boot source per MSEL pin state Bin Meng
2020-06-16 0:50 ` [PATCH v2 4/5] hw/riscv: sifive_u: Sort the SoC memmap table entries Bin Meng
2020-06-16 0:50 ` [PATCH v2 5/5] hw/riscv: sifive_u: Add a dummy DDR memory controller device Bin Meng
2020-06-16 20:23 ` [PATCH v2 0/5] hw/riscv: sifive_u: Add Mode Select (MSEL[3:0]) support Alistair Francis
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