From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <Alistair.Francis@wdc.com>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Palmer Dabbelt <palmer@dabbelt.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
"open list:RISC-V" <qemu-riscv@nongnu.org>
Subject: Re: [PATCH] riscv: sifive_u: Add a "serial" property for board serial number
Date: Fri, 22 Nov 2019 09:10:18 +0800 [thread overview]
Message-ID: <CAEUhbmUuCOzd_Y6ip_oh13gt83rM8EffdXWRCa=KybOjAvEN-A@mail.gmail.com> (raw)
In-Reply-To: <1573916930-19068-1-git-send-email-bmeng.cn@gmail.com>
On Sat, Nov 16, 2019 at 11:08 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> At present the board serial number is hard-coded to 1, and passed
> to OTP model during initialization. Firmware (FSBL, U-Boot) uses
> the serial number to generate a unique MAC address for the on-chip
> ethernet controller. When multiple QEMU 'sifive_u' instances are
> created and connected to the same subnet, they all have the same
> MAC address hence it creates a unusable network.
>
> A new "serial" property is introduced to specify the board serial
> number. When not given, the default serial number 1 is used.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> hw/riscv/sifive_u.c | 21 ++++++++++++++++++++-
> include/hw/riscv/sifive_u.h | 1 +
> 2 files changed, 21 insertions(+), 1 deletion(-)
>
ping?
next prev parent reply other threads:[~2019-11-22 1:11 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-16 15:08 [PATCH] riscv: sifive_u: Add a "serial" property for board serial number Bin Meng
2019-11-22 1:10 ` Bin Meng [this message]
2019-11-22 2:38 ` Palmer Dabbelt
2020-01-10 7:52 ` Bin Meng
2020-01-29 15:29 ` Palmer Dabbelt
2020-02-10 19:55 ` Palmer Dabbelt
2020-02-11 15:57 ` Bin Meng
2019-11-24 7:35 ` Alistair Francis
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