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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Palmer Dabbelt , "open list:RISC-V" , "qemu-devel@nongnu.org Developers" , Alistair Francis Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Thu, May 28, 2020 at 12:58 AM Alistair Francis wrote: > > Previously if we didn't enable the MMU it would be enabled in the > realize() function anyway. Let's ensure that if we don't want the MMU we > disable it. We also don't need to enable the MMU as it will be enalbed > in realize() by default. > I think we should do the same for the PMP feature as the logic is the same as MMU: PMP is always enabled in the realize() function > Signed-off-by: Alistair Francis > --- > target/riscv/cpu.c | 7 +++---- > 1 file changed, 3 insertions(+), 4 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 5eb3c02735..8deba3d16d 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -142,7 +142,6 @@ static void rv32gcsu_priv1_09_1_cpu_init(Object *obj) > set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); > set_priv_version(env, PRIV_VERSION_1_09_1); > set_resetvec(env, DEFAULT_RSTVEC); > - set_feature(env, RISCV_FEATURE_MMU); > set_feature(env, RISCV_FEATURE_PMP); > } > > @@ -152,7 +151,6 @@ static void rv32gcsu_priv1_10_0_cpu_init(Object *obj) > set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); > set_priv_version(env, PRIV_VERSION_1_10_0); > set_resetvec(env, DEFAULT_RSTVEC); > - set_feature(env, RISCV_FEATURE_MMU); > set_feature(env, RISCV_FEATURE_PMP); > } > > @@ -163,6 +161,7 @@ static void rv32imacu_nommu_cpu_init(Object *obj) > set_priv_version(env, PRIV_VERSION_1_10_0); > set_resetvec(env, DEFAULT_RSTVEC); > set_feature(env, RISCV_FEATURE_PMP); > + qdev_prop_set_bit(DEVICE(obj), "mmu", false); > } > > static void rv32imafcu_nommu_cpu_init(Object *obj) > @@ -172,6 +171,7 @@ static void rv32imafcu_nommu_cpu_init(Object *obj) > set_priv_version(env, PRIV_VERSION_1_10_0); > set_resetvec(env, DEFAULT_RSTVEC); > set_feature(env, RISCV_FEATURE_PMP); > + qdev_prop_set_bit(DEVICE(obj), "mmu", false); > } > > #elif defined(TARGET_RISCV64) > @@ -190,7 +190,6 @@ static void rv64gcsu_priv1_09_1_cpu_init(Object *obj) > set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); > set_priv_version(env, PRIV_VERSION_1_09_1); > set_resetvec(env, DEFAULT_RSTVEC); > - set_feature(env, RISCV_FEATURE_MMU); > set_feature(env, RISCV_FEATURE_PMP); > } > > @@ -200,7 +199,6 @@ static void rv64gcsu_priv1_10_0_cpu_init(Object *obj) > set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); > set_priv_version(env, PRIV_VERSION_1_10_0); > set_resetvec(env, DEFAULT_RSTVEC); > - set_feature(env, RISCV_FEATURE_MMU); > set_feature(env, RISCV_FEATURE_PMP); > } > > @@ -211,6 +209,7 @@ static void rv64imacu_nommu_cpu_init(Object *obj) > set_priv_version(env, PRIV_VERSION_1_10_0); > set_resetvec(env, DEFAULT_RSTVEC); > set_feature(env, RISCV_FEATURE_PMP); > + qdev_prop_set_bit(DEVICE(obj), "mmu", false); > } > Regards, Bin