* [PATCH v1 1/9] hw/riscv: opentitan: Update to the latest build
@ 2021-10-18 2:38 Alistair Francis
2021-10-18 2:38 ` [PATCH v1 2/9] hw/intc: Remove the Ibex PLIC Alistair Francis
` (8 more replies)
0 siblings, 9 replies; 19+ messages in thread
From: Alistair Francis @ 2021-10-18 2:38 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: bmeng.cn, palmer, alistair.francis, alistair23
From: Alistair Francis <alistair.francis@wdc.com>
Update the OpenTitan machine model to match the latest OpenTitan FPGA
design.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/opentitan.h | 6 +++---
hw/riscv/opentitan.c | 22 +++++++++++++++++-----
2 files changed, 20 insertions(+), 8 deletions(-)
diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
index 9f93bebdac..eac35ef590 100644
--- a/include/hw/riscv/opentitan.h
+++ b/include/hw/riscv/opentitan.h
@@ -20,7 +20,7 @@
#define HW_OPENTITAN_H
#include "hw/riscv/riscv_hart.h"
-#include "hw/intc/ibex_plic.h"
+#include "hw/intc/sifive_plic.h"
#include "hw/char/ibex_uart.h"
#include "hw/timer/ibex_timer.h"
#include "qom/object.h"
@@ -34,7 +34,7 @@ struct LowRISCIbexSoCState {
/*< public >*/
RISCVHartArrayState cpus;
- IbexPlicState plic;
+ SiFivePLICState plic;
IbexUartState uart;
IbexTimerState timer;
@@ -87,7 +87,7 @@ enum {
};
enum {
- IBEX_TIMER_TIMEREXPIRED0_0 = 125,
+ IBEX_TIMER_TIMEREXPIRED0_0 = 126,
IBEX_UART0_RX_PARITY_ERR_IRQ = 8,
IBEX_UART0_RX_TIMEOUT_IRQ = 7,
IBEX_UART0_RX_BREAK_ERR_IRQ = 6,
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 9803ae6d70..601f8deebe 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -46,19 +46,19 @@ static const MemMapEntry ibex_memmap[] = {
[IBEX_DEV_PINMUX] = { 0x40460000, 0x1000 },
[IBEX_DEV_PADCTRL] = { 0x40470000, 0x1000 },
[IBEX_DEV_FLASH_CTRL] = { 0x41000000, 0x1000 },
- [IBEX_DEV_PLIC] = { 0x41010000, 0x1000 },
[IBEX_DEV_AES] = { 0x41100000, 0x1000 },
[IBEX_DEV_HMAC] = { 0x41110000, 0x1000 },
[IBEX_DEV_KMAC] = { 0x41120000, 0x1000 },
- [IBEX_DEV_KEYMGR] = { 0x41130000, 0x1000 },
+ [IBEX_DEV_OTBN] = { 0x41130000, 0x10000 },
+ [IBEX_DEV_KEYMGR] = { 0x41140000, 0x1000 },
[IBEX_DEV_CSRNG] = { 0x41150000, 0x1000 },
[IBEX_DEV_ENTROPY] = { 0x41160000, 0x1000 },
[IBEX_DEV_EDNO] = { 0x41170000, 0x1000 },
[IBEX_DEV_EDN1] = { 0x41180000, 0x1000 },
[IBEX_DEV_ALERT_HANDLER] = { 0x411b0000, 0x1000 },
[IBEX_DEV_NMI_GEN] = { 0x411c0000, 0x1000 },
- [IBEX_DEV_OTBN] = { 0x411d0000, 0x10000 },
[IBEX_DEV_PERI] = { 0x411f0000, 0x10000 },
+ [IBEX_DEV_PLIC] = { 0x48000000, 0x4005000 },
[IBEX_DEV_FLASH_VIRTUAL] = { 0x80000000, 0x80000 },
};
@@ -105,7 +105,7 @@ static void lowrisc_ibex_soc_init(Object *obj)
object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
- object_initialize_child(obj, "plic", &s->plic, TYPE_IBEX_PLIC);
+ object_initialize_child(obj, "plic", &s->plic, TYPE_SIFIVE_PLIC);
object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART);
@@ -145,6 +145,18 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
&s->flash_alias);
/* PLIC */
+ qdev_prop_set_string(DEVICE(&s->plic), "hart-config", "M");
+ qdev_prop_set_uint32(DEVICE(&s->plic), "hartid-base", 0);
+ qdev_prop_set_uint32(DEVICE(&s->plic), "num-sources", 180);
+ qdev_prop_set_uint32(DEVICE(&s->plic), "num-priorities", 3);
+ qdev_prop_set_uint32(DEVICE(&s->plic), "priority-base", 0x00);
+ qdev_prop_set_uint32(DEVICE(&s->plic), "pending-base", 0x1000);
+ qdev_prop_set_uint32(DEVICE(&s->plic), "enable-base", 0x2000);
+ qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 0x18);
+ qdev_prop_set_uint32(DEVICE(&s->plic), "context-base", 0x200004);
+ qdev_prop_set_uint32(DEVICE(&s->plic), "context-stride", 4);
+ qdev_prop_set_uint32(DEVICE(&s->plic), "aperture-size", memmap[IBEX_DEV_PLIC].size);
+
if (!sysbus_realize(SYS_BUS_DEVICE(&s->plic), errp)) {
return;
}
@@ -153,7 +165,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
for (i = 0; i < ms->smp.cpus; i++) {
CPUState *cpu = qemu_get_cpu(i);
- qdev_connect_gpio_out(DEVICE(&s->plic), i,
+ qdev_connect_gpio_out(DEVICE(&s->plic), ms->smp.cpus + i,
qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT));
}
--
2.31.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v1 2/9] hw/intc: Remove the Ibex PLIC
2021-10-18 2:38 [PATCH v1 1/9] hw/riscv: opentitan: Update to the latest build Alistair Francis
@ 2021-10-18 2:38 ` Alistair Francis
2021-10-21 7:27 ` Bin Meng
2021-10-18 2:39 ` [PATCH v1 3/9] hw/intc: sifive_plic: Move the properties Alistair Francis
` (7 subsequent siblings)
8 siblings, 1 reply; 19+ messages in thread
From: Alistair Francis @ 2021-10-18 2:38 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: bmeng.cn, palmer, alistair.francis, alistair23
From: Alistair Francis <alistair.francis@wdc.com>
The Ibex PLIC is now spec complient. Let's remove the Ibex PLIC and
instead use the SiFive PLIC.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/intc/ibex_plic.c | 307 --------------------------------------------
hw/intc/meson.build | 1 -
2 files changed, 308 deletions(-)
delete mode 100644 hw/intc/ibex_plic.c
diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c
deleted file mode 100644
index ff430356f8..0000000000
--- a/hw/intc/ibex_plic.c
+++ /dev/null
@@ -1,307 +0,0 @@
-/*
- * QEMU RISC-V lowRISC Ibex PLIC
- *
- * Copyright (c) 2020 Western Digital
- *
- * Documentation avaliable: https://docs.opentitan.org/hw/ip/rv_plic/doc/
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include "qemu/osdep.h"
-#include "qemu/log.h"
-#include "hw/qdev-properties.h"
-#include "hw/core/cpu.h"
-#include "hw/boards.h"
-#include "hw/pci/msi.h"
-#include "target/riscv/cpu_bits.h"
-#include "target/riscv/cpu.h"
-#include "hw/intc/ibex_plic.h"
-#include "hw/irq.h"
-
-static bool addr_between(uint32_t addr, uint32_t base, uint32_t num)
-{
- uint32_t end = base + (num * 0x04);
-
- if (addr >= base && addr < end) {
- return true;
- }
-
- return false;
-}
-
-static void ibex_plic_irqs_set_pending(IbexPlicState *s, int irq, bool level)
-{
- int pending_num = irq / 32;
-
- if (!level) {
- /*
- * If the level is low make sure we clear the hidden_pending.
- */
- s->hidden_pending[pending_num] &= ~(1 << (irq % 32));
- }
-
- if (s->claimed[pending_num] & 1 << (irq % 32)) {
- /*
- * The interrupt has been claimed, but not completed.
- * The pending bit can't be set.
- * Save the pending level for after the interrupt is completed.
- */
- s->hidden_pending[pending_num] |= level << (irq % 32);
- } else {
- s->pending[pending_num] |= level << (irq % 32);
- }
-}
-
-static bool ibex_plic_irqs_pending(IbexPlicState *s, uint32_t context)
-{
- int i;
- uint32_t max_irq = 0;
- uint32_t max_prio = s->threshold;
-
- for (i = 0; i < s->pending_num; i++) {
- uint32_t irq_num = ctz64(s->pending[i]) + (i * 32);
-
- if (!(s->pending[i] & s->enable[i])) {
- /* No pending and enabled IRQ */
- continue;
- }
-
- if (s->priority[irq_num] > max_prio) {
- max_irq = irq_num;
- max_prio = s->priority[irq_num];
- }
- }
-
- if (max_irq) {
- s->claim = max_irq;
- return true;
- }
-
- return false;
-}
-
-static void ibex_plic_update(IbexPlicState *s)
-{
- int i;
-
- for (i = 0; i < s->num_cpus; i++) {
- qemu_set_irq(s->external_irqs[i], ibex_plic_irqs_pending(s, 0));
- }
-}
-
-static void ibex_plic_reset(DeviceState *dev)
-{
- IbexPlicState *s = IBEX_PLIC(dev);
-
- s->threshold = 0x00000000;
- s->claim = 0x00000000;
-}
-
-static uint64_t ibex_plic_read(void *opaque, hwaddr addr,
- unsigned int size)
-{
- IbexPlicState *s = opaque;
- int offset;
- uint32_t ret = 0;
-
- if (addr_between(addr, s->pending_base, s->pending_num)) {
- offset = (addr - s->pending_base) / 4;
- ret = s->pending[offset];
- } else if (addr_between(addr, s->source_base, s->source_num)) {
- qemu_log_mask(LOG_UNIMP,
- "%s: Interrupt source mode not supported\n", __func__);
- } else if (addr_between(addr, s->priority_base, s->priority_num)) {
- offset = (addr - s->priority_base) / 4;
- ret = s->priority[offset];
- } else if (addr_between(addr, s->enable_base, s->enable_num)) {
- offset = (addr - s->enable_base) / 4;
- ret = s->enable[offset];
- } else if (addr_between(addr, s->threshold_base, 1)) {
- ret = s->threshold;
- } else if (addr_between(addr, s->claim_base, 1)) {
- int pending_num = s->claim / 32;
- s->pending[pending_num] &= ~(1 << (s->claim % 32));
-
- /* Set the interrupt as claimed, but not completed */
- s->claimed[pending_num] |= 1 << (s->claim % 32);
-
- /* Return the current claimed interrupt */
- ret = s->claim;
-
- /* Clear the claimed interrupt */
- s->claim = 0x00000000;
-
- /* Update the interrupt status after the claim */
- ibex_plic_update(s);
- }
-
- return ret;
-}
-
-static void ibex_plic_write(void *opaque, hwaddr addr,
- uint64_t value, unsigned int size)
-{
- IbexPlicState *s = opaque;
-
- if (addr_between(addr, s->pending_base, s->pending_num)) {
- qemu_log_mask(LOG_GUEST_ERROR,
- "%s: Pending registers are read only\n", __func__);
- } else if (addr_between(addr, s->source_base, s->source_num)) {
- qemu_log_mask(LOG_UNIMP,
- "%s: Interrupt source mode not supported\n", __func__);
- } else if (addr_between(addr, s->priority_base, s->priority_num)) {
- uint32_t irq = ((addr - s->priority_base) >> 2) + 1;
- s->priority[irq] = value & 7;
- ibex_plic_update(s);
- } else if (addr_between(addr, s->enable_base, s->enable_num)) {
- uint32_t enable_reg = (addr - s->enable_base) / 4;
-
- s->enable[enable_reg] = value;
- } else if (addr_between(addr, s->threshold_base, 1)) {
- s->threshold = value & 3;
- } else if (addr_between(addr, s->claim_base, 1)) {
- if (s->claim == value) {
- /* Interrupt was completed */
- s->claim = 0;
- }
- if (s->claimed[value / 32] & 1 << (value % 32)) {
- int pending_num = value / 32;
-
- /* This value was already claimed, clear it. */
- s->claimed[pending_num] &= ~(1 << (value % 32));
-
- if (s->hidden_pending[pending_num] & (1 << (value % 32))) {
- /*
- * If the bit in hidden_pending is set then that means we
- * received an interrupt between claiming and completing
- * the interrupt that hasn't since been de-asserted.
- * On hardware this would trigger an interrupt, so let's
- * trigger one here as well.
- */
- s->pending[pending_num] |= 1 << (value % 32);
- }
- }
- }
-
- ibex_plic_update(s);
-}
-
-static const MemoryRegionOps ibex_plic_ops = {
- .read = ibex_plic_read,
- .write = ibex_plic_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
- .valid = {
- .min_access_size = 4,
- .max_access_size = 4
- }
-};
-
-static void ibex_plic_irq_request(void *opaque, int irq, int level)
-{
- IbexPlicState *s = opaque;
-
- ibex_plic_irqs_set_pending(s, irq, level > 0);
- ibex_plic_update(s);
-}
-
-static Property ibex_plic_properties[] = {
- DEFINE_PROP_UINT32("num-cpus", IbexPlicState, num_cpus, 1),
- DEFINE_PROP_UINT32("num-sources", IbexPlicState, num_sources, 176),
-
- DEFINE_PROP_UINT32("pending-base", IbexPlicState, pending_base, 0),
- DEFINE_PROP_UINT32("pending-num", IbexPlicState, pending_num, 6),
-
- DEFINE_PROP_UINT32("source-base", IbexPlicState, source_base, 0x18),
- DEFINE_PROP_UINT32("source-num", IbexPlicState, source_num, 6),
-
- DEFINE_PROP_UINT32("priority-base", IbexPlicState, priority_base, 0x30),
- DEFINE_PROP_UINT32("priority-num", IbexPlicState, priority_num, 177),
-
- DEFINE_PROP_UINT32("enable-base", IbexPlicState, enable_base, 0x300),
- DEFINE_PROP_UINT32("enable-num", IbexPlicState, enable_num, 6),
-
- DEFINE_PROP_UINT32("threshold-base", IbexPlicState, threshold_base, 0x318),
-
- DEFINE_PROP_UINT32("claim-base", IbexPlicState, claim_base, 0x31c),
- DEFINE_PROP_END_OF_LIST(),
-};
-
-static void ibex_plic_init(Object *obj)
-{
- IbexPlicState *s = IBEX_PLIC(obj);
-
- memory_region_init_io(&s->mmio, obj, &ibex_plic_ops, s,
- TYPE_IBEX_PLIC, 0x400);
- sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
-}
-
-static void ibex_plic_realize(DeviceState *dev, Error **errp)
-{
- IbexPlicState *s = IBEX_PLIC(dev);
- int i;
-
- s->pending = g_new0(uint32_t, s->pending_num);
- s->hidden_pending = g_new0(uint32_t, s->pending_num);
- s->claimed = g_new0(uint32_t, s->pending_num);
- s->source = g_new0(uint32_t, s->source_num);
- s->priority = g_new0(uint32_t, s->priority_num);
- s->enable = g_new0(uint32_t, s->enable_num);
-
- qdev_init_gpio_in(dev, ibex_plic_irq_request, s->num_sources);
-
- s->external_irqs = g_malloc(sizeof(qemu_irq) * s->num_cpus);
- qdev_init_gpio_out(dev, s->external_irqs, s->num_cpus);
-
- /*
- * We can't allow the supervisor to control SEIP as this would allow the
- * supervisor to clear a pending external interrupt which will result in
- * a lost interrupt in the case a PLIC is attached. The SEIP bit must be
- * hardware controlled when a PLIC is attached.
- */
- MachineState *ms = MACHINE(qdev_get_machine());
- unsigned int smp_cpus = ms->smp.cpus;
- for (i = 0; i < smp_cpus; i++) {
- RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(i));
- if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) {
- error_report("SEIP already claimed");
- exit(1);
- }
- }
-
- msi_nonbroken = true;
-}
-
-static void ibex_plic_class_init(ObjectClass *klass, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(klass);
-
- dc->reset = ibex_plic_reset;
- device_class_set_props(dc, ibex_plic_properties);
- dc->realize = ibex_plic_realize;
-}
-
-static const TypeInfo ibex_plic_info = {
- .name = TYPE_IBEX_PLIC,
- .parent = TYPE_SYS_BUS_DEVICE,
- .instance_size = sizeof(IbexPlicState),
- .instance_init = ibex_plic_init,
- .class_init = ibex_plic_class_init,
-};
-
-static void ibex_plic_register_types(void)
-{
- type_register_static(&ibex_plic_info);
-}
-
-type_init(ibex_plic_register_types)
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index a1d00aa48d..c89d2ca180 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -32,7 +32,6 @@ specific_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_nvic.c'))
specific_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_vic.c'))
specific_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210_gic.c', 'exynos4210_combiner.c'))
specific_ss.add(when: 'CONFIG_GRLIB', if_true: files('grlib_irqmp.c'))
-specific_ss.add(when: 'CONFIG_IBEX', if_true: files('ibex_plic.c'))
specific_ss.add(when: 'CONFIG_IOAPIC', if_true: files('ioapic.c'))
specific_ss.add(when: 'CONFIG_LOONGSON_LIOINTC', if_true: files('loongson_liointc.c'))
specific_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('mips_gic.c'))
--
2.31.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v1 3/9] hw/intc: sifive_plic: Move the properties
2021-10-18 2:38 [PATCH v1 1/9] hw/riscv: opentitan: Update to the latest build Alistair Francis
2021-10-18 2:38 ` [PATCH v1 2/9] hw/intc: Remove the Ibex PLIC Alistair Francis
@ 2021-10-18 2:39 ` Alistair Francis
2021-10-21 7:29 ` Bin Meng
2021-10-18 2:39 ` [PATCH v1 4/9] hw/intc: sifive_plic: Cleanup the realize function Alistair Francis
` (6 subsequent siblings)
8 siblings, 1 reply; 19+ messages in thread
From: Alistair Francis @ 2021-10-18 2:39 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: bmeng.cn, palmer, alistair.francis, alistair23
From: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/intc/sifive_plic.c | 30 +++++++++++++++---------------
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index 9ba36dc0b3..f0e2799efc 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -355,21 +355,6 @@ static const MemoryRegionOps sifive_plic_ops = {
}
};
-static Property sifive_plic_properties[] = {
- DEFINE_PROP_STRING("hart-config", SiFivePLICState, hart_config),
- DEFINE_PROP_UINT32("hartid-base", SiFivePLICState, hartid_base, 0),
- DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 0),
- DEFINE_PROP_UINT32("num-priorities", SiFivePLICState, num_priorities, 0),
- DEFINE_PROP_UINT32("priority-base", SiFivePLICState, priority_base, 0),
- DEFINE_PROP_UINT32("pending-base", SiFivePLICState, pending_base, 0),
- DEFINE_PROP_UINT32("enable-base", SiFivePLICState, enable_base, 0),
- DEFINE_PROP_UINT32("enable-stride", SiFivePLICState, enable_stride, 0),
- DEFINE_PROP_UINT32("context-base", SiFivePLICState, context_base, 0),
- DEFINE_PROP_UINT32("context-stride", SiFivePLICState, context_stride, 0),
- DEFINE_PROP_UINT32("aperture-size", SiFivePLICState, aperture_size, 0),
- DEFINE_PROP_END_OF_LIST(),
-};
-
/*
* parse PLIC hart/mode address offset config
*
@@ -496,6 +481,21 @@ static const VMStateDescription vmstate_sifive_plic = {
}
};
+static Property sifive_plic_properties[] = {
+ DEFINE_PROP_STRING("hart-config", SiFivePLICState, hart_config),
+ DEFINE_PROP_UINT32("hartid-base", SiFivePLICState, hartid_base, 0),
+ DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 0),
+ DEFINE_PROP_UINT32("num-priorities", SiFivePLICState, num_priorities, 0),
+ DEFINE_PROP_UINT32("priority-base", SiFivePLICState, priority_base, 0),
+ DEFINE_PROP_UINT32("pending-base", SiFivePLICState, pending_base, 0),
+ DEFINE_PROP_UINT32("enable-base", SiFivePLICState, enable_base, 0),
+ DEFINE_PROP_UINT32("enable-stride", SiFivePLICState, enable_stride, 0),
+ DEFINE_PROP_UINT32("context-base", SiFivePLICState, context_base, 0),
+ DEFINE_PROP_UINT32("context-stride", SiFivePLICState, context_stride, 0),
+ DEFINE_PROP_UINT32("aperture-size", SiFivePLICState, aperture_size, 0),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
static void sifive_plic_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
--
2.31.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v1 4/9] hw/intc: sifive_plic: Cleanup the realize function
2021-10-18 2:38 [PATCH v1 1/9] hw/riscv: opentitan: Update to the latest build Alistair Francis
2021-10-18 2:38 ` [PATCH v1 2/9] hw/intc: Remove the Ibex PLIC Alistair Francis
2021-10-18 2:39 ` [PATCH v1 3/9] hw/intc: sifive_plic: Move the properties Alistair Francis
@ 2021-10-18 2:39 ` Alistair Francis
2021-10-21 7:32 ` Bin Meng
2021-10-18 2:39 ` [PATCH v1 5/9] hw/intc: sifive_plic: Cleanup the irq_request function Alistair Francis
` (5 subsequent siblings)
8 siblings, 1 reply; 19+ messages in thread
From: Alistair Francis @ 2021-10-18 2:39 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: bmeng.cn, palmer, alistair.francis, alistair23
From: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/intc/sifive_plic.c | 45 +++++++++++++++++++++++--------------------
1 file changed, 24 insertions(+), 21 deletions(-)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index f0e2799efc..d77a5ced23 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -422,35 +422,38 @@ static void sifive_plic_irq_request(void *opaque, int irq, int level)
static void sifive_plic_realize(DeviceState *dev, Error **errp)
{
- SiFivePLICState *plic = SIFIVE_PLIC(dev);
+ SiFivePLICState *s = SIFIVE_PLIC(dev);
int i;
- memory_region_init_io(&plic->mmio, OBJECT(dev), &sifive_plic_ops, plic,
- TYPE_SIFIVE_PLIC, plic->aperture_size);
- parse_hart_config(plic);
- plic->bitfield_words = (plic->num_sources + 31) >> 5;
- plic->num_enables = plic->bitfield_words * plic->num_addrs;
- plic->source_priority = g_new0(uint32_t, plic->num_sources);
- plic->target_priority = g_new(uint32_t, plic->num_addrs);
- plic->pending = g_new0(uint32_t, plic->bitfield_words);
- plic->claimed = g_new0(uint32_t, plic->bitfield_words);
- plic->enable = g_new0(uint32_t, plic->num_enables);
- sysbus_init_mmio(SYS_BUS_DEVICE(dev), &plic->mmio);
- qdev_init_gpio_in(dev, sifive_plic_irq_request, plic->num_sources);
-
- plic->s_external_irqs = g_malloc(sizeof(qemu_irq) * plic->num_harts);
- qdev_init_gpio_out(dev, plic->s_external_irqs, plic->num_harts);
-
- plic->m_external_irqs = g_malloc(sizeof(qemu_irq) * plic->num_harts);
- qdev_init_gpio_out(dev, plic->m_external_irqs, plic->num_harts);
+ memory_region_init_io(&s->mmio, OBJECT(dev), &sifive_plic_ops, s,
+ TYPE_SIFIVE_PLIC, s->aperture_size);
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
+
+ parse_hart_config(s);
+
+ s->bitfield_words = (s->num_sources + 31) >> 5;
+ s->num_enables = s->bitfield_words * s->num_addrs;
+ s->source_priority = g_new0(uint32_t, s->num_sources);
+ s->target_priority = g_new(uint32_t, s->num_addrs);
+ s->pending = g_new0(uint32_t, s->bitfield_words);
+ s->claimed = g_new0(uint32_t, s->bitfield_words);
+ s->enable = g_new0(uint32_t, s->num_enables);
+
+ qdev_init_gpio_in(dev, sifive_plic_irq_request, s->num_sources);
+
+ s->s_external_irqs = g_malloc(sizeof(qemu_irq) * s->num_harts);
+ qdev_init_gpio_out(dev, s->s_external_irqs, s->num_harts);
+
+ s->m_external_irqs = g_malloc(sizeof(qemu_irq) * s->num_harts);
+ qdev_init_gpio_out(dev, s->m_external_irqs, s->num_harts);
/* We can't allow the supervisor to control SEIP as this would allow the
* supervisor to clear a pending external interrupt which will result in
* lost a interrupt in the case a PLIC is attached. The SEIP bit must be
* hardware controlled when a PLIC is attached.
*/
- for (i = 0; i < plic->num_harts; i++) {
- RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(plic->hartid_base + i));
+ for (i = 0; i < s->num_harts; i++) {
+ RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(s->hartid_base + i));
if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) {
error_report("SEIP already claimed");
exit(1);
--
2.31.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v1 5/9] hw/intc: sifive_plic: Cleanup the irq_request function
2021-10-18 2:38 [PATCH v1 1/9] hw/riscv: opentitan: Update to the latest build Alistair Francis
` (2 preceding siblings ...)
2021-10-18 2:39 ` [PATCH v1 4/9] hw/intc: sifive_plic: Cleanup the realize function Alistair Francis
@ 2021-10-18 2:39 ` Alistair Francis
2021-10-21 7:33 ` Bin Meng
2021-10-18 2:39 ` [PATCH v1 6/9] hw/intc: sifive_plic: Add a reset function Alistair Francis
` (4 subsequent siblings)
8 siblings, 1 reply; 19+ messages in thread
From: Alistair Francis @ 2021-10-18 2:39 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: bmeng.cn, palmer, alistair.francis, alistair23
From: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/intc/sifive_plic.c | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index d77a5ced23..877e76877c 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -412,12 +412,10 @@ static void parse_hart_config(SiFivePLICState *plic)
static void sifive_plic_irq_request(void *opaque, int irq, int level)
{
- SiFivePLICState *plic = opaque;
- if (RISCV_DEBUG_PLIC) {
- qemu_log("sifive_plic_irq_request: irq=%d level=%d\n", irq, level);
- }
- sifive_plic_set_pending(plic, irq, level > 0);
- sifive_plic_update(plic);
+ SiFivePLICState *s = opaque;
+
+ sifive_plic_set_pending(s, irq, level > 0);
+ sifive_plic_update(s);
}
static void sifive_plic_realize(DeviceState *dev, Error **errp)
--
2.31.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v1 6/9] hw/intc: sifive_plic: Add a reset function
2021-10-18 2:38 [PATCH v1 1/9] hw/riscv: opentitan: Update to the latest build Alistair Francis
` (3 preceding siblings ...)
2021-10-18 2:39 ` [PATCH v1 5/9] hw/intc: sifive_plic: Cleanup the irq_request function Alistair Francis
@ 2021-10-18 2:39 ` Alistair Francis
2021-10-21 7:37 ` Bin Meng
2021-10-18 2:40 ` [PATCH v1 7/9] hw/intc: sifive_plic: Cleanup the write function Alistair Francis
` (3 subsequent siblings)
8 siblings, 1 reply; 19+ messages in thread
From: Alistair Francis @ 2021-10-18 2:39 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: bmeng.cn, palmer, alistair.francis, alistair23
From: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/intc/sifive_plic.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index 877e76877c..5444368ad4 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -355,6 +355,18 @@ static const MemoryRegionOps sifive_plic_ops = {
}
};
+static void sifive_plic_reset(DeviceState *dev)
+{
+ SiFivePLICState *s = SIFIVE_PLIC(dev);
+
+ memset(s->claimed, 0, sizeof(uint32_t) * s->bitfield_words);
+ memset(s->source_priority, 0, sizeof(uint32_t) * s->num_sources);
+ memset(s->target_priority, 0, sizeof(uint32_t) * s->num_addrs);
+ memset(s->pending, 0, sizeof(uint32_t) * s->bitfield_words);
+ memset(s->claimed, 0, sizeof(uint32_t) * s->bitfield_words);
+ memset(s->enable, 0, sizeof(uint32_t) * s->num_enables);
+}
+
/*
* parse PLIC hart/mode address offset config
*
@@ -501,6 +513,7 @@ static void sifive_plic_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ dc->reset = sifive_plic_reset;
device_class_set_props(dc, sifive_plic_properties);
dc->realize = sifive_plic_realize;
dc->vmsd = &vmstate_sifive_plic;
--
2.31.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v1 7/9] hw/intc: sifive_plic: Cleanup the write function
2021-10-18 2:38 [PATCH v1 1/9] hw/riscv: opentitan: Update to the latest build Alistair Francis
` (4 preceding siblings ...)
2021-10-18 2:39 ` [PATCH v1 6/9] hw/intc: sifive_plic: Add a reset function Alistair Francis
@ 2021-10-18 2:40 ` Alistair Francis
2021-10-21 8:53 ` Bin Meng
2021-10-18 2:40 ` [PATCH v1 8/9] hw/intc: sifive_plic: Cleanup the read function Alistair Francis
` (2 subsequent siblings)
8 siblings, 1 reply; 19+ messages in thread
From: Alistair Francis @ 2021-10-18 2:40 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: bmeng.cn, palmer, alistair.francis, alistair23
From: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/intc/sifive_plic.c | 82 +++++++++++++++++--------------------------
1 file changed, 33 insertions(+), 49 deletions(-)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index 5444368ad4..49e566a76f 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -33,6 +33,17 @@
#define RISCV_DEBUG_PLIC 0
+static bool addr_between(uint32_t addr, uint32_t base, uint32_t num)
+{
+ uint32_t end = base + num;
+
+ if (addr >= base && addr < end) {
+ return true;
+ }
+
+ return false;
+}
+
static PLICMode char_to_mode(char c)
{
switch (c) {
@@ -269,80 +280,53 @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value,
{
SiFivePLICState *plic = opaque;
- /* writes must be 4 byte words */
- if ((addr & 0x3) != 0) {
- goto err;
- }
-
- if (addr >= plic->priority_base && /* 4 bytes per source */
- addr < plic->priority_base + (plic->num_sources << 2))
- {
+ if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) {
uint32_t irq = ((addr - plic->priority_base) >> 2) + 1;
+
plic->source_priority[irq] = value & 7;
- if (RISCV_DEBUG_PLIC) {
- qemu_log("plic: write priority: irq=%d priority=%d\n",
- irq, plic->source_priority[irq]);
- }
sifive_plic_update(plic);
- return;
- } else if (addr >= plic->pending_base && /* 1 bit per source */
- addr < plic->pending_base + (plic->num_sources >> 3))
- {
+ } else if (addr_between(addr, plic->pending_base,
+ plic->num_sources >> 3)) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: invalid pending write: 0x%" HWADDR_PRIx "",
__func__, addr);
- return;
- } else if (addr >= plic->enable_base && /* 1 bit per source */
- addr < plic->enable_base + plic->num_addrs * plic->enable_stride)
- {
+ } else if (addr_between(addr, plic->enable_base,
+ plic->num_addrs * plic->enable_stride)) {
uint32_t addrid = (addr - plic->enable_base) / plic->enable_stride;
uint32_t wordid = (addr & (plic->enable_stride - 1)) >> 2;
+
if (wordid < plic->bitfield_words) {
plic->enable[addrid * plic->bitfield_words + wordid] = value;
- if (RISCV_DEBUG_PLIC) {
- qemu_log("plic: write enable: hart%d-%c word=%d value=%x\n",
- plic->addr_config[addrid].hartid,
- mode_to_char(plic->addr_config[addrid].mode), wordid,
- plic->enable[addrid * plic->bitfield_words + wordid]);
- }
- return;
+ } else {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Invalid enable write 0x%" HWADDR_PRIx "\n",
+ __func__, addr);
}
- } else if (addr >= plic->context_base && /* 4 bytes per reg */
- addr < plic->context_base + plic->num_addrs * plic->context_stride)
- {
+ } else if (addr_between(addr, plic->context_base,
+ plic->num_addrs * plic->context_stride)) {
uint32_t addrid = (addr - plic->context_base) / plic->context_stride;
uint32_t contextid = (addr & (plic->context_stride - 1));
+
if (contextid == 0) {
- if (RISCV_DEBUG_PLIC) {
- qemu_log("plic: write priority: hart%d-%c priority=%x\n",
- plic->addr_config[addrid].hartid,
- mode_to_char(plic->addr_config[addrid].mode),
- plic->target_priority[addrid]);
- }
if (value <= plic->num_priorities) {
plic->target_priority[addrid] = value;
sifive_plic_update(plic);
}
- return;
} else if (contextid == 4) {
- if (RISCV_DEBUG_PLIC) {
- qemu_log("plic: write claim: hart%d-%c irq=%x\n",
- plic->addr_config[addrid].hartid,
- mode_to_char(plic->addr_config[addrid].mode),
- (uint32_t)value);
- }
if (value < plic->num_sources) {
sifive_plic_set_claimed(plic, value, false);
sifive_plic_update(plic);
}
- return;
+ } else {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Invalid context write 0x%" HWADDR_PRIx "\n",
+ __func__, addr);
}
+ } else {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Invalid register write 0x%" HWADDR_PRIx "\n",
+ __func__, addr);
}
-
-err:
- qemu_log_mask(LOG_GUEST_ERROR,
- "%s: Invalid register write 0x%" HWADDR_PRIx "\n",
- __func__, addr);
}
static const MemoryRegionOps sifive_plic_ops = {
--
2.31.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v1 8/9] hw/intc: sifive_plic: Cleanup the read function
2021-10-18 2:38 [PATCH v1 1/9] hw/riscv: opentitan: Update to the latest build Alistair Francis
` (5 preceding siblings ...)
2021-10-18 2:40 ` [PATCH v1 7/9] hw/intc: sifive_plic: Cleanup the write function Alistair Francis
@ 2021-10-18 2:40 ` Alistair Francis
2021-10-21 8:53 ` Bin Meng
2021-10-18 2:40 ` [PATCH v1 9/9] hw/intc: sifive_plic: Cleanup remaining functions Alistair Francis
2021-10-21 7:26 ` [PATCH v1 1/9] hw/riscv: opentitan: Update to the latest build Bin Meng
8 siblings, 1 reply; 19+ messages in thread
From: Alistair Francis @ 2021-10-18 2:40 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: bmeng.cn, palmer, alistair.francis, alistair23
From: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/intc/sifive_plic.c | 55 +++++++++----------------------------------
1 file changed, 11 insertions(+), 44 deletions(-)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index 49e566a76f..d73503cea4 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -205,70 +205,37 @@ static uint64_t sifive_plic_read(void *opaque, hwaddr addr, unsigned size)
{
SiFivePLICState *plic = opaque;
- /* writes must be 4 byte words */
- if ((addr & 0x3) != 0) {
- goto err;
- }
-
- if (addr >= plic->priority_base && /* 4 bytes per source */
- addr < plic->priority_base + (plic->num_sources << 2))
- {
+ if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) {
uint32_t irq = ((addr - plic->priority_base) >> 2) + 1;
- if (RISCV_DEBUG_PLIC) {
- qemu_log("plic: read priority: irq=%d priority=%d\n",
- irq, plic->source_priority[irq]);
- }
+
return plic->source_priority[irq];
- } else if (addr >= plic->pending_base && /* 1 bit per source */
- addr < plic->pending_base + (plic->num_sources >> 3))
- {
+ } else if (addr_between(addr, plic->pending_base, plic->num_sources >> 3)) {
uint32_t word = (addr - plic->pending_base) >> 2;
- if (RISCV_DEBUG_PLIC) {
- qemu_log("plic: read pending: word=%d value=%d\n",
- word, plic->pending[word]);
- }
+
return plic->pending[word];
- } else if (addr >= plic->enable_base && /* 1 bit per source */
- addr < plic->enable_base + plic->num_addrs * plic->enable_stride)
- {
+ } else if (addr_between(addr, plic->enable_base,
+ plic->num_addrs * plic->enable_stride)) {
uint32_t addrid = (addr - plic->enable_base) / plic->enable_stride;
uint32_t wordid = (addr & (plic->enable_stride - 1)) >> 2;
+
if (wordid < plic->bitfield_words) {
- if (RISCV_DEBUG_PLIC) {
- qemu_log("plic: read enable: hart%d-%c word=%d value=%x\n",
- plic->addr_config[addrid].hartid,
- mode_to_char(plic->addr_config[addrid].mode), wordid,
- plic->enable[addrid * plic->bitfield_words + wordid]);
- }
return plic->enable[addrid * plic->bitfield_words + wordid];
}
- } else if (addr >= plic->context_base && /* 1 bit per source */
- addr < plic->context_base + plic->num_addrs * plic->context_stride)
- {
+ } else if (addr_between(addr, plic->context_base,
+ plic->num_addrs * plic->context_stride)) {
uint32_t addrid = (addr - plic->context_base) / plic->context_stride;
uint32_t contextid = (addr & (plic->context_stride - 1));
+
if (contextid == 0) {
- if (RISCV_DEBUG_PLIC) {
- qemu_log("plic: read priority: hart%d-%c priority=%x\n",
- plic->addr_config[addrid].hartid,
- mode_to_char(plic->addr_config[addrid].mode),
- plic->target_priority[addrid]);
- }
return plic->target_priority[addrid];
} else if (contextid == 4) {
uint32_t value = sifive_plic_claim(plic, addrid);
- if (RISCV_DEBUG_PLIC) {
- qemu_log("plic: read claim: hart%d-%c irq=%x\n",
- plic->addr_config[addrid].hartid,
- mode_to_char(plic->addr_config[addrid].mode),
- value);
- }
+
sifive_plic_update(plic);
return value;
}
}
-err:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Invalid register read 0x%" HWADDR_PRIx "\n",
__func__, addr);
--
2.31.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v1 9/9] hw/intc: sifive_plic: Cleanup remaining functions
2021-10-18 2:38 [PATCH v1 1/9] hw/riscv: opentitan: Update to the latest build Alistair Francis
` (6 preceding siblings ...)
2021-10-18 2:40 ` [PATCH v1 8/9] hw/intc: sifive_plic: Cleanup the read function Alistair Francis
@ 2021-10-18 2:40 ` Alistair Francis
2021-10-21 8:53 ` Bin Meng
2021-10-21 7:26 ` [PATCH v1 1/9] hw/riscv: opentitan: Update to the latest build Bin Meng
8 siblings, 1 reply; 19+ messages in thread
From: Alistair Francis @ 2021-10-18 2:40 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: bmeng.cn, palmer, alistair.francis, alistair23
From: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/intc/sifive_plic.c | 109 +++++++++---------------------------------
1 file changed, 22 insertions(+), 87 deletions(-)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index d73503cea4..3f56223554 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -31,8 +31,6 @@
#include "migration/vmstate.h"
#include "hw/irq.h"
-#define RISCV_DEBUG_PLIC 0
-
static bool addr_between(uint32_t addr, uint32_t base, uint32_t num)
{
uint32_t end = base + num;
@@ -57,47 +55,6 @@ static PLICMode char_to_mode(char c)
}
}
-static char mode_to_char(PLICMode m)
-{
- switch (m) {
- case PLICMode_U: return 'U';
- case PLICMode_S: return 'S';
- case PLICMode_H: return 'H';
- case PLICMode_M: return 'M';
- default: return '?';
- }
-}
-
-static void sifive_plic_print_state(SiFivePLICState *plic)
-{
- int i;
- int addrid;
-
- /* pending */
- qemu_log("pending : ");
- for (i = plic->bitfield_words - 1; i >= 0; i--) {
- qemu_log("%08x", plic->pending[i]);
- }
- qemu_log("\n");
-
- /* pending */
- qemu_log("claimed : ");
- for (i = plic->bitfield_words - 1; i >= 0; i--) {
- qemu_log("%08x", plic->claimed[i]);
- }
- qemu_log("\n");
-
- for (addrid = 0; addrid < plic->num_addrs; addrid++) {
- qemu_log("hart%d-%c enable: ",
- plic->addr_config[addrid].hartid,
- mode_to_char(plic->addr_config[addrid].mode));
- for (i = plic->bitfield_words - 1; i >= 0; i--) {
- qemu_log("%08x", plic->enable[addrid * plic->bitfield_words + i]);
- }
- qemu_log("\n");
- }
-}
-
static uint32_t atomic_set_masked(uint32_t *a, uint32_t mask, uint32_t value)
{
uint32_t old, new, cmp = qatomic_read(a);
@@ -121,26 +78,34 @@ static void sifive_plic_set_claimed(SiFivePLICState *plic, int irq, bool level)
atomic_set_masked(&plic->claimed[irq >> 5], 1 << (irq & 31), -!!level);
}
-static int sifive_plic_irqs_pending(SiFivePLICState *plic, uint32_t addrid)
+static uint32_t sifive_plic_claimed(SiFivePLICState *plic, uint32_t addrid)
{
+ uint32_t max_irq = 0;
+ uint32_t max_prio = plic->target_priority[addrid];
int i, j;
+
for (i = 0; i < plic->bitfield_words; i++) {
uint32_t pending_enabled_not_claimed =
- (plic->pending[i] & ~plic->claimed[i]) &
- plic->enable[addrid * plic->bitfield_words + i];
+ (plic->pending[i] & ~plic->claimed[i]) &
+ plic->enable[addrid * plic->bitfield_words + i];
+
if (!pending_enabled_not_claimed) {
continue;
}
+
for (j = 0; j < 32; j++) {
int irq = (i << 5) + j;
uint32_t prio = plic->source_priority[irq];
int enabled = pending_enabled_not_claimed & (1 << j);
- if (enabled && prio > plic->target_priority[addrid]) {
- return 1;
+
+ if (enabled && prio > max_prio) {
+ max_irq = irq;
+ max_prio = prio;
}
}
}
- return 0;
+
+ return max_irq;
}
static void sifive_plic_update(SiFivePLICState *plic)
@@ -151,7 +116,7 @@ static void sifive_plic_update(SiFivePLICState *plic)
for (addrid = 0; addrid < plic->num_addrs; addrid++) {
uint32_t hartid = plic->addr_config[addrid].hartid;
PLICMode mode = plic->addr_config[addrid].mode;
- int level = sifive_plic_irqs_pending(plic, addrid);
+ bool level = !!sifive_plic_claimed(plic, addrid);
switch (mode) {
case PLICMode_M:
@@ -164,41 +129,6 @@ static void sifive_plic_update(SiFivePLICState *plic)
break;
}
}
-
- if (RISCV_DEBUG_PLIC) {
- sifive_plic_print_state(plic);
- }
-}
-
-static uint32_t sifive_plic_claim(SiFivePLICState *plic, uint32_t addrid)
-{
- int i, j;
- uint32_t max_irq = 0;
- uint32_t max_prio = plic->target_priority[addrid];
-
- for (i = 0; i < plic->bitfield_words; i++) {
- uint32_t pending_enabled_not_claimed =
- (plic->pending[i] & ~plic->claimed[i]) &
- plic->enable[addrid * plic->bitfield_words + i];
- if (!pending_enabled_not_claimed) {
- continue;
- }
- for (j = 0; j < 32; j++) {
- int irq = (i << 5) + j;
- uint32_t prio = plic->source_priority[irq];
- int enabled = pending_enabled_not_claimed & (1 << j);
- if (enabled && prio > max_prio) {
- max_irq = irq;
- max_prio = prio;
- }
- }
- }
-
- if (max_irq) {
- sifive_plic_set_pending(plic, max_irq, false);
- sifive_plic_set_claimed(plic, max_irq, true);
- }
- return max_irq;
}
static uint64_t sifive_plic_read(void *opaque, hwaddr addr, unsigned size)
@@ -229,10 +159,15 @@ static uint64_t sifive_plic_read(void *opaque, hwaddr addr, unsigned size)
if (contextid == 0) {
return plic->target_priority[addrid];
} else if (contextid == 4) {
- uint32_t value = sifive_plic_claim(plic, addrid);
+ uint32_t max_irq = sifive_plic_claimed(plic, addrid);
+
+ if (max_irq) {
+ sifive_plic_set_pending(plic, max_irq, false);
+ sifive_plic_set_claimed(plic, max_irq, true);
+ }
sifive_plic_update(plic);
- return value;
+ return max_irq;
}
}
--
2.31.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH v1 1/9] hw/riscv: opentitan: Update to the latest build
2021-10-18 2:38 [PATCH v1 1/9] hw/riscv: opentitan: Update to the latest build Alistair Francis
` (7 preceding siblings ...)
2021-10-18 2:40 ` [PATCH v1 9/9] hw/intc: sifive_plic: Cleanup remaining functions Alistair Francis
@ 2021-10-21 7:26 ` Bin Meng
8 siblings, 0 replies; 19+ messages in thread
From: Bin Meng @ 2021-10-21 7:26 UTC (permalink / raw)
To: Alistair Francis
Cc: Palmer Dabbelt, Alistair Francis, open list:RISC-V,
qemu-devel@nongnu.org Developers, Alistair Francis
On Mon, Oct 18, 2021 at 10:38 AM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> Update the OpenTitan machine model to match the latest OpenTitan FPGA
> design.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> include/hw/riscv/opentitan.h | 6 +++---
> hw/riscv/opentitan.c | 22 +++++++++++++++++-----
> 2 files changed, 20 insertions(+), 8 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v1 2/9] hw/intc: Remove the Ibex PLIC
2021-10-18 2:38 ` [PATCH v1 2/9] hw/intc: Remove the Ibex PLIC Alistair Francis
@ 2021-10-21 7:27 ` Bin Meng
0 siblings, 0 replies; 19+ messages in thread
From: Bin Meng @ 2021-10-21 7:27 UTC (permalink / raw)
To: Alistair Francis
Cc: Palmer Dabbelt, Alistair Francis, open list:RISC-V,
qemu-devel@nongnu.org Developers, Alistair Francis
On Mon, Oct 18, 2021 at 10:39 AM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> The Ibex PLIC is now spec complient. Let's remove the Ibex PLIC and
typo: compliant
> instead use the SiFive PLIC.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> hw/intc/ibex_plic.c | 307 --------------------------------------------
> hw/intc/meson.build | 1 -
> 2 files changed, 308 deletions(-)
> delete mode 100644 hw/intc/ibex_plic.c
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v1 3/9] hw/intc: sifive_plic: Move the properties
2021-10-18 2:39 ` [PATCH v1 3/9] hw/intc: sifive_plic: Move the properties Alistair Francis
@ 2021-10-21 7:29 ` Bin Meng
0 siblings, 0 replies; 19+ messages in thread
From: Bin Meng @ 2021-10-21 7:29 UTC (permalink / raw)
To: Alistair Francis
Cc: Palmer Dabbelt, Alistair Francis, open list:RISC-V,
qemu-devel@nongnu.org Developers, Alistair Francis
On Mon, Oct 18, 2021 at 10:39 AM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> hw/intc/sifive_plic.c | 30 +++++++++++++++---------------
> 1 file changed, 15 insertions(+), 15 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v1 4/9] hw/intc: sifive_plic: Cleanup the realize function
2021-10-18 2:39 ` [PATCH v1 4/9] hw/intc: sifive_plic: Cleanup the realize function Alistair Francis
@ 2021-10-21 7:32 ` Bin Meng
0 siblings, 0 replies; 19+ messages in thread
From: Bin Meng @ 2021-10-21 7:32 UTC (permalink / raw)
To: Alistair Francis
Cc: Palmer Dabbelt, Alistair Francis, open list:RISC-V,
qemu-devel@nongnu.org Developers, Alistair Francis
On Mon, Oct 18, 2021 at 10:39 AM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> hw/intc/sifive_plic.c | 45 +++++++++++++++++++++++--------------------
> 1 file changed, 24 insertions(+), 21 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v1 5/9] hw/intc: sifive_plic: Cleanup the irq_request function
2021-10-18 2:39 ` [PATCH v1 5/9] hw/intc: sifive_plic: Cleanup the irq_request function Alistair Francis
@ 2021-10-21 7:33 ` Bin Meng
2021-10-21 21:58 ` Alistair Francis
0 siblings, 1 reply; 19+ messages in thread
From: Bin Meng @ 2021-10-21 7:33 UTC (permalink / raw)
To: Alistair Francis
Cc: Palmer Dabbelt, Alistair Francis, open list:RISC-V,
qemu-devel@nongnu.org Developers, Alistair Francis
On Mon, Oct 18, 2021 at 10:39 AM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> hw/intc/sifive_plic.c | 10 ++++------
> 1 file changed, 4 insertions(+), 6 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v1 6/9] hw/intc: sifive_plic: Add a reset function
2021-10-18 2:39 ` [PATCH v1 6/9] hw/intc: sifive_plic: Add a reset function Alistair Francis
@ 2021-10-21 7:37 ` Bin Meng
0 siblings, 0 replies; 19+ messages in thread
From: Bin Meng @ 2021-10-21 7:37 UTC (permalink / raw)
To: Alistair Francis
Cc: Palmer Dabbelt, Alistair Francis, open list:RISC-V,
qemu-devel@nongnu.org Developers, Alistair Francis
On Mon, Oct 18, 2021 at 10:40 AM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> hw/intc/sifive_plic.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
> index 877e76877c..5444368ad4 100644
> --- a/hw/intc/sifive_plic.c
> +++ b/hw/intc/sifive_plic.c
> @@ -355,6 +355,18 @@ static const MemoryRegionOps sifive_plic_ops = {
> }
> };
>
> +static void sifive_plic_reset(DeviceState *dev)
> +{
> + SiFivePLICState *s = SIFIVE_PLIC(dev);
> +
> + memset(s->claimed, 0, sizeof(uint32_t) * s->bitfield_words);
This line should be removed.
> + memset(s->source_priority, 0, sizeof(uint32_t) * s->num_sources);
> + memset(s->target_priority, 0, sizeof(uint32_t) * s->num_addrs);
> + memset(s->pending, 0, sizeof(uint32_t) * s->bitfield_words);
> + memset(s->claimed, 0, sizeof(uint32_t) * s->bitfield_words);
> + memset(s->enable, 0, sizeof(uint32_t) * s->num_enables);
> +}
> +
> /*
> * parse PLIC hart/mode address offset config
> *
> @@ -501,6 +513,7 @@ static void sifive_plic_class_init(ObjectClass *klass, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(klass);
>
> + dc->reset = sifive_plic_reset;
> device_class_set_props(dc, sifive_plic_properties);
> dc->realize = sifive_plic_realize;
> dc->vmsd = &vmstate_sifive_plic;
Regards,
Bin
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v1 7/9] hw/intc: sifive_plic: Cleanup the write function
2021-10-18 2:40 ` [PATCH v1 7/9] hw/intc: sifive_plic: Cleanup the write function Alistair Francis
@ 2021-10-21 8:53 ` Bin Meng
0 siblings, 0 replies; 19+ messages in thread
From: Bin Meng @ 2021-10-21 8:53 UTC (permalink / raw)
To: Alistair Francis
Cc: Palmer Dabbelt, Alistair Francis, open list:RISC-V,
qemu-devel@nongnu.org Developers, Alistair Francis
On Mon, Oct 18, 2021 at 10:40 AM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> hw/intc/sifive_plic.c | 82 +++++++++++++++++--------------------------
> 1 file changed, 33 insertions(+), 49 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v1 8/9] hw/intc: sifive_plic: Cleanup the read function
2021-10-18 2:40 ` [PATCH v1 8/9] hw/intc: sifive_plic: Cleanup the read function Alistair Francis
@ 2021-10-21 8:53 ` Bin Meng
0 siblings, 0 replies; 19+ messages in thread
From: Bin Meng @ 2021-10-21 8:53 UTC (permalink / raw)
To: Alistair Francis
Cc: Palmer Dabbelt, Alistair Francis, open list:RISC-V,
qemu-devel@nongnu.org Developers, Alistair Francis
On Mon, Oct 18, 2021 at 10:40 AM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> hw/intc/sifive_plic.c | 55 +++++++++----------------------------------
> 1 file changed, 11 insertions(+), 44 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v1 9/9] hw/intc: sifive_plic: Cleanup remaining functions
2021-10-18 2:40 ` [PATCH v1 9/9] hw/intc: sifive_plic: Cleanup remaining functions Alistair Francis
@ 2021-10-21 8:53 ` Bin Meng
0 siblings, 0 replies; 19+ messages in thread
From: Bin Meng @ 2021-10-21 8:53 UTC (permalink / raw)
To: Alistair Francis
Cc: Palmer Dabbelt, Alistair Francis, open list:RISC-V,
qemu-devel@nongnu.org Developers, Alistair Francis
On Mon, Oct 18, 2021 at 10:40 AM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
This one needs some commit messages as it consolidates two functions
into one which is not straight forward.
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> hw/intc/sifive_plic.c | 109 +++++++++---------------------------------
> 1 file changed, 22 insertions(+), 87 deletions(-)
>
> diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
> index d73503cea4..3f56223554 100644
> --- a/hw/intc/sifive_plic.c
> +++ b/hw/intc/sifive_plic.c
> @@ -31,8 +31,6 @@
> #include "migration/vmstate.h"
> #include "hw/irq.h"
>
> -#define RISCV_DEBUG_PLIC 0
> -
> static bool addr_between(uint32_t addr, uint32_t base, uint32_t num)
> {
> uint32_t end = base + num;
> @@ -57,47 +55,6 @@ static PLICMode char_to_mode(char c)
> }
> }
>
> -static char mode_to_char(PLICMode m)
> -{
> - switch (m) {
> - case PLICMode_U: return 'U';
> - case PLICMode_S: return 'S';
> - case PLICMode_H: return 'H';
> - case PLICMode_M: return 'M';
> - default: return '?';
> - }
> -}
> -
> -static void sifive_plic_print_state(SiFivePLICState *plic)
> -{
> - int i;
> - int addrid;
> -
> - /* pending */
> - qemu_log("pending : ");
> - for (i = plic->bitfield_words - 1; i >= 0; i--) {
> - qemu_log("%08x", plic->pending[i]);
> - }
> - qemu_log("\n");
> -
> - /* pending */
> - qemu_log("claimed : ");
> - for (i = plic->bitfield_words - 1; i >= 0; i--) {
> - qemu_log("%08x", plic->claimed[i]);
> - }
> - qemu_log("\n");
> -
> - for (addrid = 0; addrid < plic->num_addrs; addrid++) {
> - qemu_log("hart%d-%c enable: ",
> - plic->addr_config[addrid].hartid,
> - mode_to_char(plic->addr_config[addrid].mode));
> - for (i = plic->bitfield_words - 1; i >= 0; i--) {
> - qemu_log("%08x", plic->enable[addrid * plic->bitfield_words + i]);
> - }
> - qemu_log("\n");
> - }
> -}
> -
> static uint32_t atomic_set_masked(uint32_t *a, uint32_t mask, uint32_t value)
> {
> uint32_t old, new, cmp = qatomic_read(a);
> @@ -121,26 +78,34 @@ static void sifive_plic_set_claimed(SiFivePLICState *plic, int irq, bool level)
> atomic_set_masked(&plic->claimed[irq >> 5], 1 << (irq & 31), -!!level);
> }
>
> -static int sifive_plic_irqs_pending(SiFivePLICState *plic, uint32_t addrid)
> +static uint32_t sifive_plic_claimed(SiFivePLICState *plic, uint32_t addrid)
> {
> + uint32_t max_irq = 0;
> + uint32_t max_prio = plic->target_priority[addrid];
> int i, j;
> +
> for (i = 0; i < plic->bitfield_words; i++) {
> uint32_t pending_enabled_not_claimed =
> - (plic->pending[i] & ~plic->claimed[i]) &
> - plic->enable[addrid * plic->bitfield_words + i];
> + (plic->pending[i] & ~plic->claimed[i]) &
> + plic->enable[addrid * plic->bitfield_words + i];
> +
> if (!pending_enabled_not_claimed) {
> continue;
> }
> +
> for (j = 0; j < 32; j++) {
> int irq = (i << 5) + j;
> uint32_t prio = plic->source_priority[irq];
> int enabled = pending_enabled_not_claimed & (1 << j);
> - if (enabled && prio > plic->target_priority[addrid]) {
> - return 1;
> +
> + if (enabled && prio > max_prio) {
> + max_irq = irq;
> + max_prio = prio;
> }
> }
> }
> - return 0;
> +
> + return max_irq;
> }
>
> static void sifive_plic_update(SiFivePLICState *plic)
> @@ -151,7 +116,7 @@ static void sifive_plic_update(SiFivePLICState *plic)
> for (addrid = 0; addrid < plic->num_addrs; addrid++) {
> uint32_t hartid = plic->addr_config[addrid].hartid;
> PLICMode mode = plic->addr_config[addrid].mode;
> - int level = sifive_plic_irqs_pending(plic, addrid);
> + bool level = !!sifive_plic_claimed(plic, addrid);
>
> switch (mode) {
> case PLICMode_M:
> @@ -164,41 +129,6 @@ static void sifive_plic_update(SiFivePLICState *plic)
> break;
> }
> }
> -
> - if (RISCV_DEBUG_PLIC) {
> - sifive_plic_print_state(plic);
> - }
> -}
> -
> -static uint32_t sifive_plic_claim(SiFivePLICState *plic, uint32_t addrid)
> -{
> - int i, j;
> - uint32_t max_irq = 0;
> - uint32_t max_prio = plic->target_priority[addrid];
> -
> - for (i = 0; i < plic->bitfield_words; i++) {
> - uint32_t pending_enabled_not_claimed =
> - (plic->pending[i] & ~plic->claimed[i]) &
> - plic->enable[addrid * plic->bitfield_words + i];
> - if (!pending_enabled_not_claimed) {
> - continue;
> - }
> - for (j = 0; j < 32; j++) {
> - int irq = (i << 5) + j;
> - uint32_t prio = plic->source_priority[irq];
> - int enabled = pending_enabled_not_claimed & (1 << j);
> - if (enabled && prio > max_prio) {
> - max_irq = irq;
> - max_prio = prio;
> - }
> - }
> - }
> -
> - if (max_irq) {
> - sifive_plic_set_pending(plic, max_irq, false);
> - sifive_plic_set_claimed(plic, max_irq, true);
> - }
> - return max_irq;
> }
>
> static uint64_t sifive_plic_read(void *opaque, hwaddr addr, unsigned size)
> @@ -229,10 +159,15 @@ static uint64_t sifive_plic_read(void *opaque, hwaddr addr, unsigned size)
> if (contextid == 0) {
> return plic->target_priority[addrid];
> } else if (contextid == 4) {
> - uint32_t value = sifive_plic_claim(plic, addrid);
> + uint32_t max_irq = sifive_plic_claimed(plic, addrid);
> +
> + if (max_irq) {
> + sifive_plic_set_pending(plic, max_irq, false);
> + sifive_plic_set_claimed(plic, max_irq, true);
> + }
>
> sifive_plic_update(plic);
> - return value;
> + return max_irq;
> }
> }
>
Regards,
Bin
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v1 5/9] hw/intc: sifive_plic: Cleanup the irq_request function
2021-10-21 7:33 ` Bin Meng
@ 2021-10-21 21:58 ` Alistair Francis
0 siblings, 0 replies; 19+ messages in thread
From: Alistair Francis @ 2021-10-21 21:58 UTC (permalink / raw)
To: Bin Meng
Cc: open list:RISC-V, Alistair Francis, Palmer Dabbelt,
Alistair Francis, qemu-devel@nongnu.org Developers
On Thu, Oct 21, 2021 at 5:33 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Mon, Oct 18, 2021 at 10:39 AM Alistair Francis
> <alistair.francis@opensource.wdc.com> wrote:
> >
> > From: Alistair Francis <alistair.francis@wdc.com>
> >
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > ---
> > hw/intc/sifive_plic.c | 10 ++++------
> > 1 file changed, 4 insertions(+), 6 deletions(-)
> >
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Thanks!
Applied this and earlier patches to riscv-to-apply.next
Alistair
^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2021-10-21 22:05 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-10-18 2:38 [PATCH v1 1/9] hw/riscv: opentitan: Update to the latest build Alistair Francis
2021-10-18 2:38 ` [PATCH v1 2/9] hw/intc: Remove the Ibex PLIC Alistair Francis
2021-10-21 7:27 ` Bin Meng
2021-10-18 2:39 ` [PATCH v1 3/9] hw/intc: sifive_plic: Move the properties Alistair Francis
2021-10-21 7:29 ` Bin Meng
2021-10-18 2:39 ` [PATCH v1 4/9] hw/intc: sifive_plic: Cleanup the realize function Alistair Francis
2021-10-21 7:32 ` Bin Meng
2021-10-18 2:39 ` [PATCH v1 5/9] hw/intc: sifive_plic: Cleanup the irq_request function Alistair Francis
2021-10-21 7:33 ` Bin Meng
2021-10-21 21:58 ` Alistair Francis
2021-10-18 2:39 ` [PATCH v1 6/9] hw/intc: sifive_plic: Add a reset function Alistair Francis
2021-10-21 7:37 ` Bin Meng
2021-10-18 2:40 ` [PATCH v1 7/9] hw/intc: sifive_plic: Cleanup the write function Alistair Francis
2021-10-21 8:53 ` Bin Meng
2021-10-18 2:40 ` [PATCH v1 8/9] hw/intc: sifive_plic: Cleanup the read function Alistair Francis
2021-10-21 8:53 ` Bin Meng
2021-10-18 2:40 ` [PATCH v1 9/9] hw/intc: sifive_plic: Cleanup remaining functions Alistair Francis
2021-10-21 8:53 ` Bin Meng
2021-10-21 7:26 ` [PATCH v1 1/9] hw/riscv: opentitan: Update to the latest build Bin Meng
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