From: Bin Meng <bmeng.cn@gmail.com>
To: Ivan Griffin <ivan.griffin@emdalo.com>
Cc: QEMU Trivial <qemu-trivial@nongnu.org>,
Alistair Francis <alistair23@gmail.com>,
Bin Meng <bin.meng@windriver.com>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>
Subject: Re: [PATCH] hw/riscv: microchip_pfsoc: IOSCBCTRL memmap entry
Date: Mon, 19 Oct 2020 10:05:12 +0800 [thread overview]
Message-ID: <CAEUhbmVPzOuP3kuMhZB2JgN47nnzL7p9+meyhyBK7kRAhu5BCw@mail.gmail.com> (raw)
In-Reply-To: <DB7PR10MB191544AA04D0B3ECF82C57CDFE030@DB7PR10MB1915.EURPRD10.PROD.OUTLOOK.COM>
Hi Ivan,
On Sat, Oct 17, 2020 at 12:31 AM Ivan Griffin <ivan.griffin@emdalo.com> wrote:
>
> I don't know why it isn't documented in that PDF (or in the register map), but if you check https://github.com/polarfire-soc/polarfire-soc-bare-metal-library/blob/master/src/platform/drivers/mss_sys_services/mss_sys_services.h you'll see the following
>
> ```
> typedef struct
> {
> volatile uint32_t SOFT_RESET;
> volatile uint32_t VDETECTOR;
> volatile uint32_t TVS_CONTROL;
> volatile uint32_t TVS_TEMP_A;
> volatile uint32_t TVS_TEMP_B;
> volatile uint32_t TVS_TEMP_C;
> volatile uint32_t TVS_VOLT_A;
> volatile uint32_t TVS_VOLT_B;
> volatile uint32_t TVS_VOLT_C;
> volatile uint32_t TVS_OUTPUT0;
> volatile uint32_t TVS_OUTPUT1;
> volatile uint32_t TVS_TRIGGER;
> volatile uint32_t TRIM_VDET1P05;
> volatile uint32_t TRIM_VDET1P8;
> volatile uint32_t TRIM_VDET2P5;
> volatile uint32_t TRIM_TVS;
> volatile uint32_t TRIM_GDET1P05;
> volatile uint32_t RESERVED0;
> volatile uint32_t RESERVED1;
> volatile uint32_t RESERVED2;
> volatile uint32_t SERVICES_CR;
> volatile uint32_t SERVICES_SR;
> volatile uint32_t USER_DETECTOR_SR;
> volatile uint32_t USER_DETECTOR_CR;
> volatile uint32_t MSS_SPI_CR;
>
> } SCBCTRL_TypeDef;
>
> #define MSS_SCBCTRL ((SCBCTRL_TypeDef*) (0x37020000UL))
>
> /*2kB bytes long mailbox.*/
> #define MSS_SCBMAILBOX ((uint32_t*) (0x37020800UL))
> ```
>
> And in https://github.com/polarfire-soc/polarfire-soc-bare-metal-library/blob/master/src/platform/drivers/mss_sys_services/mss_sys_services.c you'll see MSS_SCB and MSS_SCBMAILBOX used in many places to interact with the FPGA system controller to perform various services.
It's actually documented, but not in the PDF file. I also spent some
time locating the doc when I do the DDR controller modeling work.
See Register Map/PF_SoC_RegMap_V1_1/MPFS250T/pfsoc_control_scb.htm in
https://www.microsemi.com/document-portal/doc_download/1244581-polarfire-soc-register-map
Regards,
Bin
next prev parent reply other threads:[~2020-10-19 2:06 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-16 12:37 [PATCH] hw/riscv: microchip_pfsoc: IOSCBCTRL memmap entry Ivan Griffin
2020-10-16 16:07 ` Alistair Francis
2020-10-16 16:31 ` Ivan Griffin
2020-10-16 16:24 ` Alistair Francis
2020-10-16 17:10 ` [PATCH v2] " Ivan Griffin
2020-10-16 17:37 ` Alistair Francis
2020-10-19 1:57 ` Bin Meng
2020-10-27 20:56 ` Alistair Francis
2020-10-19 2:05 ` Bin Meng [this message]
2020-10-19 8:17 ` [PATCH] " Ivan Griffin
2020-10-19 8:38 ` Bin Meng
2020-10-19 8:42 ` Ivan Griffin
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