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X-Received-From: 2a00:1450:4864:20::543 Subject: Re: [Qemu-devel] [Qemu-riscv] [PATCH] riscv: sifive_e: Correct various SoC IP block sizes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:RISC-V" , Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , "qemu-devel@nongnu.org Developers" , Chih-Min Chao , Alistair Francis Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Hi Palmer, On Wed, Aug 7, 2019 at 10:53 AM Bin Meng wrote: > > On Wed, Aug 7, 2019 at 5:06 AM Philippe Mathieu-Daud=C3=A9 wrote: > > > > On 8/5/19 8:43 AM, Bin Meng wrote: > > > On Mon, Aug 5, 2019 at 2:14 PM Chih-Min Chao wrote: > > >> On Sat, Aug 3, 2019 at 8:27 AM Bin Meng wrote: > > >>> > > >>> Some of the SoC IP block sizes are wrong. Correct them according > > >>> to the FE310 manual. > > >>> > > >>> Signed-off-by: Bin Meng > > >>> --- > > >>> > > >>> hw/riscv/sifive_e.c | 6 +++--- > > >>> 1 file changed, 3 insertions(+), 3 deletions(-) > > >>> > > >>> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c > > >>> index 2a499d8..9655847 100644 > > >>> --- a/hw/riscv/sifive_e.c > > >>> +++ b/hw/riscv/sifive_e.c > > >>> @@ -53,13 +53,13 @@ static const struct MemmapEntry { > > >>> hwaddr base; > > >>> hwaddr size; > > >>> } sifive_e_memmap[] =3D { > > >>> - [SIFIVE_E_DEBUG] =3D { 0x0, 0x100 }, > > >>> + [SIFIVE_E_DEBUG] =3D { 0x0, 0x1000 }, > > >>> [SIFIVE_E_MROM] =3D { 0x1000, 0x2000 }, > > >>> [SIFIVE_E_OTP] =3D { 0x20000, 0x2000 }, > > >>> [SIFIVE_E_CLINT] =3D { 0x2000000, 0x10000 }, > > >>> [SIFIVE_E_PLIC] =3D { 0xc000000, 0x4000000 }, > > >>> - [SIFIVE_E_AON] =3D { 0x10000000, 0x8000 }, > > >>> - [SIFIVE_E_PRCI] =3D { 0x10008000, 0x8000 }, > > >>> + [SIFIVE_E_AON] =3D { 0x10000000, 0x1000 }, > > >>> + [SIFIVE_E_PRCI] =3D { 0x10008000, 0x1000 }, > > >>> [SIFIVE_E_OTP_CTRL] =3D { 0x10010000, 0x1000 }, > > >>> [SIFIVE_E_GPIO0] =3D { 0x10012000, 0x1000 }, > > >>> [SIFIVE_E_UART0] =3D { 0x10013000, 0x1000 }, > > >>> -- > > >>> 2.7.4 > > >>> > > >> > > >> It seems the modification follows E310-G002(Hifive1 Rev B) spec and= the origin is for E310-G000(Hifive1) spec. > > >> There should be some way to specify different board version with dif= ferent memory map or we have policy, always support the latest spec. > > > > I agree with Chao, it would be cleaner to have two different boards > > (machines). > > Since the SoCs are very similar, you could add a 'revision' property an= d > > use it to select the correct map. > > > > I am not sure if adding two different machines will bring us a lot of > benefits, since the only difference is the SoC revision with different > block sizes. > > > >> > > > > > > Yes, I checked both specs. The older spec says these bigger sizes, > > > however their register sizes fit well in the smaller range as well. S= o > > > I think the modification works well for both. > > > > This is OK for the PRCI, since sifive_prci_create() does not use > > memmap[SIFIVE_E_PRCI].size. > > > > However the AON case is borderline, since you shrink it from 32KiB to 4= KiB. > > > > AON is not implemented anyway currently. And I checked the FE310 old > spec, its register block size is still within the 4KiB range, so > shrinking the size should be fine for both old and new SoC. > > > BTW (not related to this patch) it is odd a function named > > sifive_mmio_emulate() creates a RAM region with memory_region_init_ram(= ) > > and does not use the UnimplementedDevice (see make_unimp_dev() in > > hw/arm/musca.c). > > What's your suggestion regarding this patch? Regards, Bin