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charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::b34; envelope-from=bmeng.cn@gmail.com; helo=mail-yb1-xb34.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , "open list:RISC-V" , Sagar Karandikar , Anup Patel , "qemu-devel@nongnu.org Developers" , Atish Patra , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Tue, Nov 2, 2021 at 6:24 PM Anup Patel wrote: > > On Tue, Nov 2, 2021 at 12:22 PM Bin Meng wrote: > > > > On Tue, Oct 26, 2021 at 2:43 PM Anup Patel wrote: > > > > > > A hypervsior can optionally take guest external interrupts using > > > > typo: hypervisor > > Okay, I will update. > > > > > > SGEIP bit of hip and hie CSRs. > > > > > > Signed-off-by: Anup Patel > > > Reviewed-by: Alistair Francis > > > --- > > > target/riscv/cpu.c | 3 ++- > > > target/riscv/cpu_bits.h | 3 +++ > > > target/riscv/csr.c | 18 +++++++++++------- > > > 3 files changed, 16 insertions(+), 8 deletions(-) > > > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > > index 788fa0b11c..0460a3972b 100644 > > > --- a/target/riscv/cpu.c > > > +++ b/target/riscv/cpu.c > > > @@ -365,6 +365,7 @@ static void riscv_cpu_reset(DeviceState *dev) > > > env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); > > > } > > > env->mcause = 0; > > > + env->miclaim = MIP_SGEIP; > > > env->pc = env->resetvec; > > > env->two_stage_lookup = false; > > > #endif > > > @@ -598,7 +599,7 @@ static void riscv_cpu_init(Object *obj) > > > cpu_set_cpustate_pointers(cpu); > > > > > > #ifndef CONFIG_USER_ONLY > > > - qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 12); > > > + qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, IRQ_LOCAL_MAX); > > > #endif /* CONFIG_USER_ONLY */ > > > } > > > > > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > > > index cffcd3a5df..8a5a4cde95 100644 > > > --- a/target/riscv/cpu_bits.h > > > +++ b/target/riscv/cpu_bits.h > > > @@ -498,6 +498,8 @@ typedef enum RISCVException { > > > #define IRQ_S_EXT 9 > > > #define IRQ_VS_EXT 10 > > > #define IRQ_M_EXT 11 > > > +#define IRQ_S_GEXT 12 > > > +#define IRQ_LOCAL_MAX 13 > > > > The IRQ_LOCAL_MAX should be XLEN long, not 13. > > The IRQ_LOCAL_MAX here represents local interrupts > standardized by the RISC-V privilege spec. This value The standardardized IRQ number is 16. > will change only when more local interrupts are > standardized by the RISC-V privilege spec. We should leave room for platform / custom IRQ as it is already defined by the priv spec. Regards, Bin