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Wed, 24 Mar 2021 20:40:31 -0700 (PDT) MIME-Version: 1.0 References: <20210323091409.1226-1-dylan@andestech.com> <20210325033121.GA9484@andestech.com> In-Reply-To: <20210325033121.GA9484@andestech.com> From: Bin Meng Date: Thu, 25 Mar 2021 11:40:19 +0800 Message-ID: Subject: Re: [PATCH] target/riscv: Align the data type of reset vector address To: Dylan Jhong Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=bmeng.cn@gmail.com; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:RISC-V" , Sagar Karandikar , =?UTF-8?B?QWxhbiBRdWV5LUxpYW5nIEthbyjpq5jprYHoia8p?= , Bastian Koppelmann , "qemu-devel@nongnu.org Developers" , Alistair Francis , "x5710999x@gmail.com" , =?UTF-8?B?UnVpbmxhbmQgQ2h1YW4tVHp1IFRzYSjolKHlgrPos4cp?= , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Thu, Mar 25, 2021 at 11:32 AM Dylan Jhong wrote: > > On Wed, Mar 24, 2021 at 10:59:55PM +0800, Alistair Francis wrote: > > On Tue, Mar 23, 2021 at 5:15 AM Dylan Jhong wrote: > > > > > > Although the AE350 has not been upstream (preparing for v2), > > > the reset vector of the AE350 is known to be at the 2G position, > > > so this patch is corrected in advance. > > > > > > Signed-off-by: Dylan Jhong > > > Signed-off-by: Ruinland ChuanTzu Tsai > > > --- > > > target/riscv/cpu.c | 2 +- > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > > index 2a990f6253..0236abf169 100644 > > > --- a/target/riscv/cpu.c > > > +++ b/target/riscv/cpu.c > > > @@ -137,7 +137,7 @@ static void set_feature(CPURISCVState *env, int feature) > > > env->features |= (1ULL << feature); > > > } > > > > > > -static void set_resetvec(CPURISCVState *env, int resetvec) > > > +static void set_resetvec(CPURISCVState *env, uint64_t resetvec) > > > > resetvec in env is a target_ulong so this should be as well (instead > > of a uint64_t). > > > > Alistair > > > > Hi Alistar, > > Thanks for your comments. > > Indeed resetvec should use target_ulong instead of uint64_t. resetvec being target_ulong means that rv32 cannot have a reset vector beyond 4GiB. I don't think the spec disallow this. > But in target/riscv/cpu.h:306, there is also a resetvec in struct RISCVCPU but it is defined as uint64_t. > Do you think I should change it to target_ulong together? > > ref: > commit 9b4c9b2b2a50fe4eb90d0ac2d8723b46ecb42511 > https://www.mail-archive.com/qemu-devel@nongnu.org/msg730077.html Regards, Bin