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From: Bin Meng <bmeng.cn@gmail.com>
To: Dylan Jhong <dylan@andestech.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
	"Sagar Karandikar" <sagark@eecs.berkeley.edu>,
	"Alan Quey-Liang Kao(高魁良)" <alankao@andestech.com>,
	"Bastian Koppelmann" <kbastian@mail.uni-paderborn.de>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	"Alistair Francis" <alistair.francis@wdc.com>,
	"x5710999x@gmail.com" <x5710999x@gmail.com>,
	"Ruinland Chuan-Tzu Tsa(蔡傳資)" <ruinland@andestech.com>,
	"Alistair Francis" <alistair23@gmail.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>
Subject: Re: [PATCH] target/riscv: Align the data type of reset vector address
Date: Thu, 25 Mar 2021 11:59:44 +0800	[thread overview]
Message-ID: <CAEUhbmXK3aniZtqXDFKkGvz=M36eaNmTZhEyceOFrFkBLX0J1A@mail.gmail.com> (raw)
In-Reply-To: <CAEUhbmWr6+fSHyM2RJUmoB7Np7Y4pY3J_dvsDAZEVpt6ceiRiw@mail.gmail.com>

On Thu, Mar 25, 2021 at 11:40 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Thu, Mar 25, 2021 at 11:32 AM Dylan Jhong <dylan@andestech.com> wrote:
> >
> > On Wed, Mar 24, 2021 at 10:59:55PM +0800, Alistair Francis wrote:
> > > On Tue, Mar 23, 2021 at 5:15 AM Dylan Jhong <dylan@andestech.com> wrote:
> > > >
> > > > Although the AE350 has not been upstream (preparing for v2),
> > > > the reset vector of the AE350 is known to be at the 2G position,
> > > > so this patch is corrected in advance.
> > > >
> > > > Signed-off-by: Dylan Jhong <dylan@andestech.com>
> > > > Signed-off-by: Ruinland ChuanTzu Tsai <ruinland@andestech.com>
> > > > ---
> > > >  target/riscv/cpu.c | 2 +-
> > > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > > >
> > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > > > index 2a990f6253..0236abf169 100644
> > > > --- a/target/riscv/cpu.c
> > > > +++ b/target/riscv/cpu.c
> > > > @@ -137,7 +137,7 @@ static void set_feature(CPURISCVState *env, int feature)
> > > >      env->features |= (1ULL << feature);
> > > >  }
> > > >
> > > > -static void set_resetvec(CPURISCVState *env, int resetvec)
> > > > +static void set_resetvec(CPURISCVState *env, uint64_t resetvec)
> > >
> > > resetvec in env is a target_ulong so this should be as well (instead
> > > of a uint64_t).
> > >
> > > Alistair
> > >
> >
> > Hi Alistar,
> >
> > Thanks for your comments.
> >
> > Indeed resetvec should use target_ulong instead of uint64_t.
>
> resetvec being target_ulong means that rv32 cannot have a reset vector
> beyond 4GiB. I don't think the spec disallow this.

Ah, I was wrong. The spec says: "the pc is set to an implementation-de
ned reset vector" and pc is XLEN wide.

So for rv32 the reset vector cannot beyond 4GiB. We should change it
to target_ulong.

Regards,
Bin


      reply	other threads:[~2021-03-25  4:01 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-23  9:14 [PATCH] target/riscv: Align the data type of reset vector address Dylan Jhong
2021-03-24 14:59 ` Alistair Francis
2021-03-25  3:31   ` Dylan Jhong
2021-03-25  3:40     ` Bin Meng
2021-03-25  3:59       ` Bin Meng [this message]

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