From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <alistair.francis@wdc.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Alistair Francis <alistair23@gmail.com>
Subject: Re: [PATCH v1 1/1] hw/opentitan: Update the interrupt layout
Date: Tue, 6 Apr 2021 16:32:02 +0800 [thread overview]
Message-ID: <CAEUhbmXLHVck3ee1v_DR4WCNxjW7Uhw4VKQ4jv9U37aBtqTySw@mail.gmail.com> (raw)
In-Reply-To: <e92b696f1809c9fa4410da2e9f23c414db5a6960.1617202791.git.alistair.francis@wdc.com>
On Wed, Mar 31, 2021 at 11:02 PM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> Update the OpenTitan interrupt layout to match the latest OpenTitan
> bitstreams. This involves changing the Ibex PLIC memory layout and the
> UART interrupts.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> include/hw/riscv/opentitan.h | 16 ++++++++--------
> hw/intc/ibex_plic.c | 20 ++++++++++----------
> hw/riscv/opentitan.c | 8 ++++----
> 3 files changed, 22 insertions(+), 22 deletions(-)
>
LGTM
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
next prev parent reply other threads:[~2021-04-06 8:34 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-31 15:00 [PATCH v1 1/1] hw/opentitan: Update the interrupt layout Alistair Francis
2021-04-06 8:32 ` Bin Meng [this message]
2021-04-07 14:25 ` Alistair Francis
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