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From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <alistair.francis@wdc.com>
Cc: weiying_hou@outlook.com,
	"open list:RISC-V" <qemu-riscv@nongnu.org>,
	Ethan.Lee.QNL@gmail.com,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Alistair Francis <alistair23@gmail.com>,
	camiyoru@gmail.com
Subject: Re: [PATCH v1 2/8] target/riscv: Define ePMP mseccfg
Date: Wed, 7 Apr 2021 22:24:22 +0800	[thread overview]
Message-ID: <CAEUhbmXyyQYAL3fxE0tO094BO-Ry+BO0GW4nZX9fS9jLri_x7A@mail.gmail.com> (raw)
In-Reply-To: <5bf4e802b52fc4f8e57c8c03346cec716ea3ce32.1617367533.git.alistair.francis@wdc.com>

On Fri, Apr 2, 2021 at 8:49 PM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> From: Hou Weiying <weiying_hou@outlook.com>
>
> Use address  0x390 and 0x391 for the ePMP CSRs.

nits: remove one space before 0x390

>
> Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
> Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
> Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> Message-Id: <SG2PR02MB2634D85E5DF0C2BB540AE1BB93450@SG2PR02MB2634.apcprd02.prod.outlook.com>
> [ Changes by AF:
>  - Tidy up commit message
> ]
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>  target/riscv/cpu_bits.h | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index caf4599207..32e1ee92dc 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -232,6 +232,9 @@
>  #define CSR_MTINST          0x34a
>  #define CSR_MTVAL2          0x34b
>
> +/* Enhanced PMP */

nits: Enhanced Physical Memory Protection ?

> +#define CSR_MSECCFG         0x390
> +#define CSR_MSECCFGH        0x391
>  /* Physical Memory Protection */
>  #define CSR_PMPCFG0         0x3a0
>  #define CSR_PMPCFG1         0x3a1

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Regards,
Bin


  reply	other threads:[~2021-04-07 14:26 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-02 12:47 [PATCH v1 0/8] RISC-V: Add support for ePMP v0.9.1 Alistair Francis
2021-04-02 12:47 ` [PATCH v1 1/8] target/riscv: Fix the PMP is locked check when using TOR Alistair Francis
2021-04-08  9:25   ` Bin Meng
2021-04-02 12:47 ` [PATCH v1 2/8] target/riscv: Define ePMP mseccfg Alistair Francis
2021-04-07 14:24   ` Bin Meng [this message]
2021-04-02 12:47 ` [PATCH v1 3/8] target/riscv: Add the ePMP feature Alistair Francis
2021-04-07 14:24   ` Bin Meng
2021-04-02 12:47 ` [PATCH v1 4/8] target/riscv: Add ePMP CSR access functions Alistair Francis
2021-04-08 12:57   ` Bin Meng
2021-04-02 12:48 ` [PATCH v1 5/8] target/riscv: Implementation of enhanced PMP (ePMP) Alistair Francis
2021-04-09  4:24   ` Bin Meng
2021-04-11 23:03     ` Alistair Francis
2021-04-02 12:48 ` [PATCH v1 6/8] target/riscv: Add a config option for ePMP Alistair Francis
2021-04-07 14:28   ` Bin Meng
2021-04-02 12:48 ` [PATCH v1 7/8] target/riscv/pmp: Remove outdated comment Alistair Francis
2021-04-07 14:28   ` Bin Meng
2021-04-02 12:48 ` [PATCH v1 8/8] target/riscv: Add ePMP support for the Ibex CPU Alistair Francis
2021-04-07 14:28   ` Bin Meng

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