From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 77115C433EF for ; Mon, 18 Oct 2021 06:13:24 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C154E60F9E for ; Mon, 18 Oct 2021 06:13:23 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org C154E60F9E Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:33054 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mcLti-0003UV-KT for qemu-devel@archiver.kernel.org; Mon, 18 Oct 2021 02:13:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34166) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcLq8-0001gl-LZ for qemu-devel@nongnu.org; Mon, 18 Oct 2021 02:09:40 -0400 Received: from mail-io1-xd34.google.com ([2607:f8b0:4864:20::d34]:35627) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mcLq5-0006Rf-9i for qemu-devel@nongnu.org; Mon, 18 Oct 2021 02:09:40 -0400 Received: by mail-io1-xd34.google.com with SMTP id h196so14933816iof.2 for ; Sun, 17 Oct 2021 23:09:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=oY1zmJUGMV+k6zW8u/A583+W7qjgsIGSgC3SOGdNGlU=; b=nH3iHYCyY98Vp/draVeJmn1Ea9PiqW9WzwidJdWwAvZfPz79bviN7LUx1mct2dqR1s NnI1ncGp1SwqxDnENsP+yqTJwdoweiVxP8U0mhSIqHyXQiaP1871mQTCK7h2SXoKEtLl 2ZsfuhVqQWUhA+pSp4wrRS6Y8YsS87E7C6ygl6WZQSWaOBcuNG8tdHpetgLqoJXwJMHA 4WMoIKsStuOhukRRnB7eCIuK4pO1ggwdkGHWM9Se4QNiuSITcEkpU84rS4KxlaRm1Jqb jrzCd3B5df/qKYy/pK7jk66E1+Qdp5FyCTC5yJjaBSQicBlxT11b3aMJXEs1w0SIsGho UT+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=oY1zmJUGMV+k6zW8u/A583+W7qjgsIGSgC3SOGdNGlU=; b=bjDJHNtROn5Of+vJ780mzfFQ8aUbA2MwoS+P3yA/PehXJLm5SnxKhUZv6V2A7WdPjh 2W7JMft65ARLHTxD29J+WMLX2xDndZP3iAwLKuBZHz/VySeH/pmGgnlhB70cnHDSZTur 4fb8bBfwIOSp5tYmNjjpNV5R/rXMCCIFqUf/UgcJIJiRuARObL8nnGl1WFxNIhEzPktE BLtvtLFbvvxV0+nK3PcY5Y8Tt9mJjK9EHow6w/DX2C/MTF/rFJo5gOcsXOm25Wy3PGe+ Q8/OywL6ioX5MYtS29L8FgzQ6nkrDUyFwJY6z54ze/B6zS45QTYyCSbkLP3M9EKuaEMs DYhg== X-Gm-Message-State: AOAM533Q9cMoNdJ2/cH40SSIyruNJ9i5sLtsouVoHiwA2U0tdD6ZNK++ xAOv9j/vzsI3vRZop9joEKiRU4H3LzVNz+IUdOjw3w== X-Google-Smtp-Source: ABdhPJwTCqYmWNvYnEnfYzUcX4a3Po4wQ2Bgmp2M5ES6X3ACnEw78Cd6vGJJZyR5q+n2PRWJ4LO6uJclanPe845SvlQ= X-Received: by 2002:a5d:9256:: with SMTP id e22mr13010686iol.152.1634537375898; Sun, 17 Oct 2021 23:09:35 -0700 (PDT) MIME-Version: 1.0 References: <20211015074627.3957162-1-frank.chang@sifive.com> In-Reply-To: From: Frank Chang Date: Mon, 18 Oct 2021 14:09:24 +0800 Message-ID: Subject: Re: [PATCH v8 00/78] support vector extension v1.0 To: Alistair Francis Content-Type: multipart/alternative; boundary="000000000000a9b7e705ce9a63b2" Received-SPF: pass client-ip=2607:f8b0:4864:20::d34; envelope-from=frank.chang@sifive.com; helo=mail-io1-xd34.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:RISC-V" , "qemu-devel@nongnu.org Developers" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --000000000000a9b7e705ce9a63b2 Content-Type: text/plain; charset="UTF-8" On Mon, Oct 18, 2021 at 2:00 PM Alistair Francis wrote: > On Fri, Oct 15, 2021 at 5:48 PM wrote: > > > > From: Frank Chang > > > > This patchset implements the vector extension v1.0 for RISC-V on QEMU. > > > > RVV v1.0 spec is now fronzen for public review: > > https://github.com/riscv/riscv-v-spec/releases/tag/v1.0 > > > > The port is available here: > > https://github.com/sifive/qemu/tree/rvv-1.0-upstream-v8 > > > > RVV v1.0 can be enabled with -cpu option: v=true and specify vext_spec > > option to v1.0 (i.e. vext_spec=v1.0) > > It doesn't seem like this series made it to the general QEMU list. You > might want to check to see what happened there. > > Hi Alistair, what does "general QEMU list" mean here? Regards, Frank Chang Alistair > > > > > Note: This patchset depends on other patchsets listed in Based-on > > section below so it is not able to be built unless those patchsets > > are applied. > > > > Changelog: > > > > v8 > > * Use {get,dest}_gpr APIs. > > * remove vector AMO instructions. > > * rename vpopc.m to vcpop.m. > > * rename vle1.v and vse1.v to vlm.v and vsm.v. > > * rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm. > > > > v7 > > * remove hardcoded GDB vector registers list. > > * add vsetivli instruction. > > * add vle1.v and vse1.v instructions. > > > > v6 > > * add vector floating-point reciprocal estimate instruction. > > * add vector floating-point reciprocal square-root estimate > instruction. > > * update check rules for segment register groups, each segment register > > group has to follow overlap rules. > > * update viota.m instruction check rules. > > > > v5 > > * refactor RVV v1.0 check functions. > > (Thanks to Richard Henderson's bitwise tricks.) > > * relax RV_VLEN_MAX to 1024-bits. > > * implement vstart CSR's behaviors. > > * trigger illegal instruction exception if frm is not valid for > > vector floating-point instructions. > > * rebase on riscv-to-apply.next. > > > > v4 > > * remove explicit float flmul variable in DisasContext. > > * replace floating-point calculations with shift operations to > > improve performance. > > * relax RV_VLEN_MAX to 512-bits. > > > > v3 > > * apply nan-box helpers from Richard Henderson. > > * remove fp16 api changes as they are sent independently in another > > pathcset by Chih-Min Chao. > > * remove all tail elements clear functions as tail elements can > > retain unchanged for either VTA set to undisturbed or agnostic. > > * add fp16 nan-box check generator function. > > * add floating-point rounding mode enum. > > * replace flmul arithmetic with shifts to avoid floating-point > > conversions. > > * add Zvqmac extension. > > * replace gdbstub vector register xml files with dynamic generator. > > * bumped to RVV v1.0. > > * RVV v1.0 related changes: > > * add vlre.v and vsr.v vector whole register > > load/store instructions > > * add vrgatherei16 instruction. > > * rearranged bits in vtype to make vlmul bits into a contiguous > > field. > > > > v2 > > * drop v0.7.1 support. > > * replace invisible return check macros with functions. > > * move mark_vs_dirty() to translators. > > * add SSTATUS_VS flag for s-mode. > > * nan-box scalar fp register for floating-point operations. > > * add gdbstub files for vector registers to allow system-mode > > debugging with GDB. > > > > Based-on: <20211015065500.3850513-1-frank.chang@sifive.com> > > Based-on: <20211015070307.3860984-1-frank.chang@sifive.com> > > > > Frank Chang (73): > > target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh > > target/riscv: drop vector 0.7.1 and add 1.0 support > > target/riscv: Use FIELD_EX32() to extract wd field > > target/riscv: rvv-1.0: introduce writable misa.v field > > target/riscv: rvv-1.0: add translation-time vector context status > > target/riscv: rvv-1.0: remove rvv related codes from fcsr registers > > target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr > > registers > > target/riscv: rvv-1.0: remove MLEN calculations > > target/riscv: rvv-1.0: add fractional LMUL > > target/riscv: rvv-1.0: add VMA and VTA > > target/riscv: rvv-1.0: update check functions > > target/riscv: introduce more imm value modes in translator functions > > target/riscv: rvv:1.0: add translation-time nan-box helper function > > target/riscv: rvv-1.0: remove amo operations instructions > > target/riscv: rvv-1.0: configure instructions > > target/riscv: rvv-1.0: stride load and store instructions > > target/riscv: rvv-1.0: index load and store instructions > > target/riscv: rvv-1.0: fix address index overflow bug of indexed > > load/store insns > > target/riscv: rvv-1.0: fault-only-first unit stride load > > target/riscv: rvv-1.0: load/store whole register instructions > > target/riscv: rvv-1.0: update vext_max_elems() for load/store insns > > target/riscv: rvv-1.0: take fractional LMUL into vector max elements > > calculation > > target/riscv: rvv-1.0: floating-point square-root instruction > > target/riscv: rvv-1.0: floating-point classify instructions > > target/riscv: rvv-1.0: count population in mask instruction > > target/riscv: rvv-1.0: find-first-set mask bit instruction > > target/riscv: rvv-1.0: set-X-first mask bit instructions > > target/riscv: rvv-1.0: iota instruction > > target/riscv: rvv-1.0: element index instruction > > target/riscv: rvv-1.0: allow load element with sign-extended > > target/riscv: rvv-1.0: register gather instructions > > target/riscv: rvv-1.0: integer scalar move instructions > > target/riscv: rvv-1.0: floating-point move instruction > > target/riscv: rvv-1.0: floating-point scalar move instructions > > target/riscv: rvv-1.0: whole register move instructions > > target/riscv: rvv-1.0: integer extension instructions > > target/riscv: rvv-1.0: single-width averaging add and subtract > > instructions > > target/riscv: rvv-1.0: single-width bit shift instructions > > target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow > > target/riscv: rvv-1.0: narrowing integer right shift instructions > > target/riscv: rvv-1.0: widening integer multiply-add instructions > > target/riscv: rvv-1.0: single-width saturating add and subtract > > instructions > > target/riscv: rvv-1.0: integer comparison instructions > > target/riscv: rvv-1.0: floating-point compare instructions > > target/riscv: rvv-1.0: mask-register logical instructions > > target/riscv: rvv-1.0: slide instructions > > target/riscv: rvv-1.0: floating-point slide instructions > > target/riscv: rvv-1.0: narrowing fixed-point clip instructions > > target/riscv: rvv-1.0: single-width floating-point reduction > > target/riscv: rvv-1.0: widening floating-point reduction instructions > > target/riscv: rvv-1.0: single-width scaling shift instructions > > target/riscv: rvv-1.0: remove widening saturating scaled multiply-add > > target/riscv: rvv-1.0: remove vmford.vv and vmford.vf > > target/riscv: rvv-1.0: remove integer extract instruction > > target/riscv: rvv-1.0: floating-point min/max instructions > > target/riscv: introduce floating-point rounding mode enum > > target/riscv: rvv-1.0: floating-point/integer type-convert > > instructions > > target/riscv: rvv-1.0: widening floating-point/integer type-convert > > target/riscv: add "set round to odd" rounding mode helper function > > target/riscv: rvv-1.0: narrowing floating-point/integer type-convert > > target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits > > target/riscv: rvv-1.0: implement vstart CSR > > target/riscv: rvv-1.0: trigger illegal instruction exception if frm is > > not valid > > target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs > > target/riscv: rvv-1.0: floating-point reciprocal square-root estimate > > instruction > > target/riscv: rvv-1.0: floating-point reciprocal estimate instruction > > target/riscv: set mstatus.SD bit when writing fp CSRs > > target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11 > > target/riscv: rvv-1.0: add vsetivli instruction > > target/riscv: rvv-1.0: add evl parameter to vext_ldst_us() > > target/riscv: rvv-1.0: add vector unit-stride mask load/store insns > > target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm > > and vmorn.mm > > target/riscv: rvv-1.0: update opivv_vadc_check() comment > > > > Greentime Hu (1): > > target/riscv: rvv-1.0: add vlenb register > > > > Hsiangkai Wang (1): > > target/riscv: gdb: support vector registers for rv64 & rv32 > > > > LIU Zhiwei (3): > > target/riscv: rvv-1.0: add mstatus VS field > > target/riscv: rvv-1.0: add sstatus VS field > > target/riscv: rvv-1.0: add vcsr register > > > > target/riscv/cpu.c | 12 +- > > target/riscv/cpu.h | 85 +- > > target/riscv/cpu_bits.h | 10 + > > target/riscv/cpu_helper.c | 15 +- > > target/riscv/csr.c | 92 +- > > target/riscv/fpu_helper.c | 17 +- > > target/riscv/gdbstub.c | 184 ++ > > target/riscv/helper.h | 435 ++- > > target/riscv/insn32.decode | 294 +- > > target/riscv/insn_trans/trans_rvv.c.inc | 2423 +++++++++------ > > target/riscv/internals.h | 24 +- > > target/riscv/translate.c | 74 +- > > target/riscv/vector_helper.c | 3601 ++++++++++++----------- > > 13 files changed, 4176 insertions(+), 3090 deletions(-) > > > > -- > > 2.25.1 > > > > > --000000000000a9b7e705ce9a63b2 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
On Mon, Oct 18, 2021 at 2:00 PM Alistair = Francis <alistair23@gmail.com> wrote:
On Fri, Oct 15, 2021 at 5:48 PM <frank.chang@sifive.com>= wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> This patchset implements the vector extension v1.0 for RISC-V on QEMU.=
>
> RVV v1.0 spec is now fronzen for public review:
> https://github.com/riscv/riscv-v-spec/re= leases/tag/v1.0
>
> The port is available here:
> https://github.com/sifive/qemu/tree/rvv-= 1.0-upstream-v8
>
> RVV v1.0 can be enabled with -cpu option: v=3Dtrue and specify vext_sp= ec
> option to v1.0 (i.e. vext_spec=3Dv1.0)

It doesn't seem like this series made it to the general QEMU list. You<= br> might want to check to see what happened there.


Hi Alistair, what does "general Q= EMU list" mean here?

Regards,
Frank= Chang

vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm.
>
> v7
>=C2=A0 =C2=A0* remove hardcoded GDB vector registers list.
>=C2=A0 =C2=A0* add vsetivli instruction.
>=C2=A0 =C2=A0* add vle1.v and vse1.v instructions.
>
> v6
>=C2=A0 =C2=A0* add vector floating-point reciprocal estimate instructio= n.
>=C2=A0 =C2=A0* add vector floating-point reciprocal square-root estimat= e instruction.
>=C2=A0 =C2=A0* update check rules for segment register groups, each seg= ment register
>=C2=A0 =C2=A0 =C2=A0group has to follow overlap rules.
>=C2=A0 =C2=A0* update viota.m instruction check rules.
>
> v5
>=C2=A0 =C2=A0* refactor RVV v1.0 check functions.
>=C2=A0 =C2=A0 =C2=A0(Thanks to Richard Henderson's bitwise tricks.)=
>=C2=A0 =C2=A0* relax RV_VLEN_MAX to 1024-bits.
>=C2=A0 =C2=A0* implement vstart CSR's behaviors.
>=C2=A0 =C2=A0* trigger illegal instruction exception if frm is not vali= d for
>=C2=A0 =C2=A0 =C2=A0vector floating-point instructions.
>=C2=A0 =C2=A0* rebase on riscv-to-apply.next.
>
> v4
>=C2=A0 =C2=A0* remove explicit float flmul variable in DisasContext. >=C2=A0 =C2=A0* replace floating-point calculations with shift operation= s to
>=C2=A0 =C2=A0 =C2=A0improve performance.
>=C2=A0 =C2=A0* relax RV_VLEN_MAX to 512-bits.
>
> v3
>=C2=A0 =C2=A0* apply nan-box helpers from Richard Henderson.
>=C2=A0 =C2=A0* remove fp16 api changes as they are sent independently i= n another
>=C2=A0 =C2=A0 =C2=A0pathcset by Chih-Min Chao.
>=C2=A0 =C2=A0* remove all tail elements clear functions as tail element= s can
>=C2=A0 =C2=A0 =C2=A0retain unchanged for either VTA set to undisturbed = or agnostic.
>=C2=A0 =C2=A0* add fp16 nan-box check generator function.
>=C2=A0 =C2=A0* add floating-point rounding mode enum.
>=C2=A0 =C2=A0* replace flmul arithmetic with shifts to avoid floating-p= oint
>=C2=A0 =C2=A0 =C2=A0conversions.
>=C2=A0 =C2=A0* add Zvqmac extension.
>=C2=A0 =C2=A0* replace gdbstub vector register xml files with dynamic g= enerator.
>=C2=A0 =C2=A0* bumped to RVV v1.0.
>=C2=A0 =C2=A0* RVV v1.0 related changes:
>=C2=A0 =C2=A0 =C2=A0* add vl<nf>re<eew>.v and vs<nf>r= .v vector whole register
>=C2=A0 =C2=A0 =C2=A0 =C2=A0load/store instructions
>=C2=A0 =C2=A0 =C2=A0* add vrgatherei16 instruction.
>=C2=A0 =C2=A0 =C2=A0* rearranged bits in vtype to make vlmul bits into = a contiguous
>=C2=A0 =C2=A0 =C2=A0 =C2=A0field.
>
> v2
>=C2=A0 =C2=A0* drop v0.7.1 support.
>=C2=A0 =C2=A0* replace invisible return check macros with functions. >=C2=A0 =C2=A0* move mark_vs_dirty() to translators.
>=C2=A0 =C2=A0* add SSTATUS_VS flag for s-mode.
>=C2=A0 =C2=A0* nan-box scalar fp register for floating-point operations= .
>=C2=A0 =C2=A0* add gdbstub files for vector registers to allow system-m= ode
>=C2=A0 =C2=A0 =C2=A0debugging with GDB.
>
> Based-on: <20211015065500.3850513-1-frank.chang@sifive.co= m>
> Based-on: <20211015070307.3860984-1-frank.chang@sifive.co= m>
>
> Frank Chang (73):
>=C2=A0 =C2=A0target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rv= h
>=C2=A0 =C2=A0target/riscv: drop vector 0.7.1 and add 1.0 support
>=C2=A0 =C2=A0target/riscv: Use FIELD_EX32() to extract wd field
>=C2=A0 =C2=A0target/riscv: rvv-1.0: introduce writable misa.v field
>=C2=A0 =C2=A0target/riscv: rvv-1.0: add translation-time vector context= status
>=C2=A0 =C2=A0target/riscv: rvv-1.0: remove rvv related codes from fcsr = registers
>=C2=A0 =C2=A0target/riscv: rvv-1.0: check MSTATUS_VS when accessing vec= tor csr
>=C2=A0 =C2=A0 =C2=A0registers
>=C2=A0 =C2=A0target/riscv: rvv-1.0: remove MLEN calculations
>=C2=A0 =C2=A0target/riscv: rvv-1.0: add fractional LMUL
>=C2=A0 =C2=A0target/riscv: rvv-1.0: add VMA and VTA
>=C2=A0 =C2=A0target/riscv: rvv-1.0: update check functions
>=C2=A0 =C2=A0target/riscv: introduce more imm value modes in translator= functions
>=C2=A0 =C2=A0target/riscv: rvv:1.0: add translation-time nan-box helper= function
>=C2=A0 =C2=A0target/riscv: rvv-1.0: remove amo operations instructions<= br> >=C2=A0 =C2=A0target/riscv: rvv-1.0: configure instructions
>=C2=A0 =C2=A0target/riscv: rvv-1.0: stride load and store instructions<= br> >=C2=A0 =C2=A0target/riscv: rvv-1.0: index load and store instructions >=C2=A0 =C2=A0target/riscv: rvv-1.0: fix address index overflow bug of i= ndexed
>=C2=A0 =C2=A0 =C2=A0load/store insns
>=C2=A0 =C2=A0target/riscv: rvv-1.0: fault-only-first unit stride load >=C2=A0 =C2=A0target/riscv: rvv-1.0: load/store whole register instructi= ons
>=C2=A0 =C2=A0target/riscv: rvv-1.0: update vext_max_elems() for load/st= ore insns
>=C2=A0 =C2=A0target/riscv: rvv-1.0: take fractional LMUL into vector ma= x elements
>=C2=A0 =C2=A0 =C2=A0calculation
>=C2=A0 =C2=A0target/riscv: rvv-1.0: floating-point square-root instruct= ion
>=C2=A0 =C2=A0target/riscv: rvv-1.0: floating-point classify instruction= s
>=C2=A0 =C2=A0target/riscv: rvv-1.0: count population in mask instructio= n
>=C2=A0 =C2=A0target/riscv: rvv-1.0: find-first-set mask bit instruction=
>=C2=A0 =C2=A0target/riscv: rvv-1.0: set-X-first mask bit instructions >=C2=A0 =C2=A0target/riscv: rvv-1.0: iota instruction
>=C2=A0 =C2=A0target/riscv: rvv-1.0: element index instruction
>=C2=A0 =C2=A0target/riscv: rvv-1.0: allow load element with sign-extend= ed
>=C2=A0 =C2=A0target/riscv: rvv-1.0: register gather instructions
>=C2=A0 =C2=A0target/riscv: rvv-1.0: integer scalar move instructions >=C2=A0 =C2=A0target/riscv: rvv-1.0: floating-point move instruction
>=C2=A0 =C2=A0target/riscv: rvv-1.0: floating-point scalar move instruct= ions
>=C2=A0 =C2=A0target/riscv: rvv-1.0: whole register move instructions >=C2=A0 =C2=A0target/riscv: rvv-1.0: integer extension instructions
>=C2=A0 =C2=A0target/riscv: rvv-1.0: single-width averaging add and subt= ract
>=C2=A0 =C2=A0 =C2=A0instructions
>=C2=A0 =C2=A0target/riscv: rvv-1.0: single-width bit shift instructions=
>=C2=A0 =C2=A0target/riscv: rvv-1.0: integer add-with-carry/subtract-wit= h-borrow
>=C2=A0 =C2=A0target/riscv: rvv-1.0: narrowing integer right shift instr= uctions
>=C2=A0 =C2=A0target/riscv: rvv-1.0: widening integer multiply-add instr= uctions
>=C2=A0 =C2=A0target/riscv: rvv-1.0: single-width saturating add and sub= tract
>=C2=A0 =C2=A0 =C2=A0instructions
>=C2=A0 =C2=A0target/riscv: rvv-1.0: integer comparison instructions
>=C2=A0 =C2=A0target/riscv: rvv-1.0: floating-point compare instructions=
>=C2=A0 =C2=A0target/riscv: rvv-1.0: mask-register logical instructions<= br> >=C2=A0 =C2=A0target/riscv: rvv-1.0: slide instructions
>=C2=A0 =C2=A0target/riscv: rvv-1.0: floating-point slide instructions >=C2=A0 =C2=A0target/riscv: rvv-1.0: narrowing fixed-point clip instruct= ions
>=C2=A0 =C2=A0target/riscv: rvv-1.0: single-width floating-point reducti= on
>=C2=A0 =C2=A0target/riscv: rvv-1.0: widening floating-point reduction i= nstructions
>=C2=A0 =C2=A0target/riscv: rvv-1.0: single-width scaling shift instruct= ions
>=C2=A0 =C2=A0target/riscv: rvv-1.0: remove widening saturating scaled m= ultiply-add
>=C2=A0 =C2=A0target/riscv: rvv-1.0: remove vmford.vv and vmford.vf
>=C2=A0 =C2=A0target/riscv: rvv-1.0: remove integer extract instruction<= br> >=C2=A0 =C2=A0target/riscv: rvv-1.0: floating-point min/max instructions=
>=C2=A0 =C2=A0target/riscv: introduce floating-point rounding mode enum<= br> >=C2=A0 =C2=A0target/riscv: rvv-1.0: floating-point/integer type-convert=
>=C2=A0 =C2=A0 =C2=A0instructions
>=C2=A0 =C2=A0target/riscv: rvv-1.0: widening floating-point/integer typ= e-convert
>=C2=A0 =C2=A0target/riscv: add "set round to odd" rounding mo= de helper function
>=C2=A0 =C2=A0target/riscv: rvv-1.0: narrowing floating-point/integer ty= pe-convert
>=C2=A0 =C2=A0target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits
>=C2=A0 =C2=A0target/riscv: rvv-1.0: implement vstart CSR
>=C2=A0 =C2=A0target/riscv: rvv-1.0: trigger illegal instruction excepti= on if frm is
>=C2=A0 =C2=A0 =C2=A0not valid
>=C2=A0 =C2=A0target/riscv: rvv-1.0: set mstatus.SD bit when writing vec= tor CSRs
>=C2=A0 =C2=A0target/riscv: rvv-1.0: floating-point reciprocal square-ro= ot estimate
>=C2=A0 =C2=A0 =C2=A0instruction
>=C2=A0 =C2=A0target/riscv: rvv-1.0: floating-point reciprocal estimate = instruction
>=C2=A0 =C2=A0target/riscv: set mstatus.SD bit when writing fp CSRs
>=C2=A0 =C2=A0target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11
>=C2=A0 =C2=A0target/riscv: rvv-1.0: add vsetivli instruction
>=C2=A0 =C2=A0target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()=
>=C2=A0 =C2=A0target/riscv: rvv-1.0: add vector unit-stride mask load/st= ore insns
>=C2=A0 =C2=A0target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm<= br> >=C2=A0 =C2=A0 =C2=A0and vmorn.mm
>=C2=A0 =C2=A0target/riscv: rvv-1.0: update opivv_vadc_check() comment >
> Greentime Hu (1):
>=C2=A0 =C2=A0target/riscv: rvv-1.0: add vlenb register
>
> Hsiangkai Wang (1):
>=C2=A0 =C2=A0target/riscv: gdb: support vector registers for rv64 &= rv32
>
> LIU Zhiwei (3):
>=C2=A0 =C2=A0target/riscv: rvv-1.0: add mstatus VS field
>=C2=A0 =C2=A0target/riscv: rvv-1.0: add sstatus VS field
>=C2=A0 =C2=A0target/riscv: rvv-1.0: add vcsr register
>
>=C2=A0 target/riscv/cpu.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A012 +-
>=C2=A0 target/riscv/cpu.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A085 +-
>=C2=A0 target/riscv/cpu_bits.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2=A010 +
>=C2=A0 target/riscv/cpu_helper.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0|=C2=A0 =C2=A015 +-
>=C2=A0 target/riscv/csr.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A092 +-
>=C2=A0 target/riscv/fpu_helper.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0|=C2=A0 =C2=A017 +-
>=C2=A0 target/riscv/gdbstub.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 |=C2=A0 184 ++
>=C2=A0 target/riscv/helper.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 435 ++-
>=C2=A0 target/riscv/insn32.decode=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 |=C2=A0 294 +-
>=C2=A0 target/riscv/insn_trans/trans_rvv.c.inc | 2423 +++++++++------ >=C2=A0 target/riscv/internals.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A024 +-
>=C2=A0 target/riscv/translate.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A074 +-
>=C2=A0 target/riscv/vector_helper.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 | 3601 ++++++++++++-----------
>=C2=A0 13 files changed, 4176 insertions(+), 3090 deletions(-)
>
> --
> 2.25.1
>
>
--000000000000a9b7e705ce9a63b2--