qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Frank Chang <frank.chang@sifive.com>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: "Alex Bennée" <alex.bennee@linaro.org>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"open list:RISC-V" <qemu-riscv@nongnu.org>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	"Aurelien Jarno" <aurelien@aurel32.net>
Subject: Re: [PATCH] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions
Date: Tue, 20 Apr 2021 09:18:01 +0800	[thread overview]
Message-ID: <CAE_xrPhW1eE_-yLXd3J4vovCKeq3xtHDXB1Dn5kQe3c5gSgjwA@mail.gmail.com> (raw)
In-Reply-To: <448d86ca-28b0-6523-d84b-4f9e867cf01b@linaro.org>

[-- Attachment #1: Type: text/plain, Size: 1074 bytes --]

On Mon, Apr 19, 2021 at 11:28 PM Richard Henderson <
richard.henderson@linaro.org> wrote:

> On 4/18/21 10:56 PM, frank.chang@sifive.com wrote:
> > +#elif defined(TARGET_RISCV)
> > +    /*
> > +     * For RISC-V, InvalidOp is set when multiplicands are Inf and zero
> > +     * and returns default NaN.
> > +     */
> > +    if (infzero) {
> > +        float_raise(float_flag_invalid, status);
> > +        return 3;
> > +    }
> > +
> > +    if (is_nan(a_cls)) {
> > +        return 0;
> > +    } else if (is_nan(b_cls)) {
> > +        return 1;
> > +    } else {
> > +        return 2;
> > +    }
>
> This second half of the function made me go look into the spec to make
> sure you
> had got that selection right.  But RISCV is always in default_nan mode, so
> all
> this is unused (and overridden in pick_nan_muladd).
>
> I think for avoidance of confusion, you should use
>
>      if (infzero) {
>          float_raise(float_flag_invalid, status);
>      }
>      return 3; /* default nan */
>
>
> r~
>

Sure, I'll update my patch and resend again.

Thanks
Frank Chang

[-- Attachment #2: Type: text/html, Size: 1666 bytes --]

      reply	other threads:[~2021-04-20  1:19 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-19  5:56 [PATCH] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions frank.chang
2021-04-19 15:28 ` Richard Henderson
2021-04-20  1:18   ` Frank Chang [this message]

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=CAE_xrPhW1eE_-yLXd3J4vovCKeq3xtHDXB1Dn5kQe3c5gSgjwA@mail.gmail.com \
    --to=frank.chang@sifive.com \
    --cc=alex.bennee@linaro.org \
    --cc=aurelien@aurel32.net \
    --cc=peter.maydell@linaro.org \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-riscv@nongnu.org \
    --cc=richard.henderson@linaro.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).